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? 2008 microchip technology inc. ds22091a-page 1 mcp454x/456x/464x/466x features ? single or dual resistor network options ? potentiometer or rheostat configuration options ? resistor network resolution - 7-bit: 128 resistors (129 steps) - 8-bit: 256 resistors (257 steps) ?r ab resistances options of: -5k -10k -50k - 100 k ? zero-scale to full-scale wiper operation ? low wiper resistance: 75 (typ.) ? low tempco: - absolute (rheostat): 50 ppm typical (0c to 70c) - ratiometric (potentiometer): 15 ppm typical ? non-volatile memory - automatic recall of saved wiper setting - wiperlock? technology - 10 general purpose memory locations ?i 2 c serial interface - (100 khz, 400 khz and 3.4 mhz support) - internal weak pull-up on sda and scl pins ? serial protocol allows: - high-speed read/write to wiper - read/write to eeprom - write protect to be enabled/disabled - wiperlock to be enabled/disabled ? resistor network terminal disconnect feature via the terminal control (tcon) register ? write protect feature: - hardware write protect (wp ) control pin - software write protect (wp) configuration bit ? brown-out reset protection (1.5v typical) ? serial interface inactive current (2.5 ua typ.) ? high-voltage tolerant digital inputs: up to 12.5v ? internal weak pull-up on all digital inputs ? wide operating voltage: - 2.7v to 5.5v - device characteristics specified - 1.8v to 5.5v - device operation ? wide bandwidth (-3db) operation: - 2 mhz (typ.) for 5.0 k device ? extended temperature range (-40c to +125c) description the mcp45xx and mcp46xx devices offer a wide range of product offerings using an i 2 c interface. this family of devices support 7-bit and 8-bit resistor networks, non-volatile memory configurations, and potentiometer and rheostat pinouts. wiperlock technology a llows application-specific calibration settings to be secured in the eeprom. package types 1 2 3 4 5 6 7 8 p0w p0b p0a v ss v dd mcp45x1 single potentiometer dfn 3x3 (mf), msop hvc / a0 sda scl 1 2 3 4 5 6 7 8 p0b a1 p0w v dd dfn 3x3 (mf), msop 1 2 3 4 11 12 13 14 a2 a1 wp v dd mcp46x1 dual potentiometers tssop 5 6 7 8 9 10 p0w p0b p0a p1a p1w p1b v ss hvc / a0 sda scl v ss hvc / a0 sda scl 1 2 3 4 11 12 13 14 a1 a2 qfn-16 4x4 (ml) 5 6 78 9 10 p0b nc p0w p0a p1a p1w v ss scl v ss sda 15 16 p1b v dd hvc/a0 wp 1 2 3 4 7 8 9 10 a1 v dd mcp46x2 dual rheostat dfn 3x3 (mf), msop 5 6 p0b p0w p1w p1b v ss hvc / a0 sda scl mcp45x2 single rheostat 7/8-bit single/dual i 2 c digital pot with non-volatile memory
mcp454x/456x/464x/466x ds22091a-page 2 ? 2008 microchip technology inc. device block diagram device features device # of pots wiper configuration control interface memory type wiperlock technology por wiper setting resistance (typical) # of steps v dd operating range (2) r ab options (k ) wiper - r w ( ) mcp4531 (3) 1 potentiometer (1) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4532 (3) 1 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4541 1 potentiometer (1) i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 129 2.7v to 5.5v mcp4542 1 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 129 2.7v to 5.5v mcp4551 (3) 1 potentiometer (1) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4552 (3) 1 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4561 1 potentiometer (1) i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 257 2.7v to 5.5v mcp4562 1 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 257 2.7v to 5.5v mcp4631 (3) 2 potentiometer (1) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4632 (3) 2 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 129 1.8v to 5.5v mcp4641 2 potentiometer (1) i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 129 2.7v to 5.5v mcp4642 2 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 129 2.7v to 5.5v mcp4651 (3) 2 potentiometer (1) i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4652 (3) 2 rheostat i 2 c ram no mid-scale 5.0, 10.0, 50.0, 100.0 75 257 1.8v to 5.5v mcp4661 2 potentiometer (1) i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 257 2.7v to 5.5v mcp4662 2 rheostat i 2 c ee yes nv wiper 5.0, 10.0, 50 .0, 100.0 75 257 2.7v to 5.5v note 1: floating either terminal (a or b) allows the devi ce to be used as a rheostat (variable resistor). 2: analog characteristics only tested from 2.7v to 5.5v unless otherwise noted. 3: please check microchip web site for device release and availability power-up/ brown-out control v dd v ss i 2 c serial interface module & control logic (wiperlock? technology) resistor network 0 (pot 0) wiper 0 & tcon register resistor network 1 (pot 1) wiper 1 & tcon register a2 a1 hvc/a0 scl sda wp memory (16x9) wiper0 (v & nv) wiper1 (v & nv) tcon status data eeprom (10 x 9-bits) p0a p0w p0b p1a p1w p1b for dual resistor network devices only i 2 c interface
? 2008 microchip technology inc. ds22091a-page 3 mcp454x/456x/464x/466x 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss ............... -0.6v to +7.0v voltage on hvc/a0, a1, a2, scl, sda, and wp with respect to v ss ............................................................. -0.6v to 12.5v voltage on all other pins (pxa, pxw, and pxb) with respect to v ss ......................................... -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd , v i > v pp on hv pins) ......................20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ..................................................20 ma maximum output current sunk by any output pin ......................................................................................25 ma maximum output current sourced by any output pin ......................................................................................25 ma maximum current out of v ss pin .................................100 ma maximum current into v dd pin ....................................100 ma maximum current into p x a, p x w & p x b pins ............2.5 ma storage temperature ....................................-65c to +150c ambient temperature with power applied -40c to +125c total power dissipation ( note 1 ) ................................400 mw soldering temperature of leads (10 seconds) ............. +300c esd protection on all pins .................................. 4 kv (hbm), .......................................................................... 300v (mm) maximum junction temperature (t j ) ......................... +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent dam age to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol )
mcp454x/456x/464x/466x ds22091a-page 4 ? 2008 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions supply voltage v dd 2.7 ? 5.5 v 1.8 ? 2.7 v serial interface only. hvc pin voltage range v hv v ss ? 12.5v v v dd 4.5v the hvc pin will be at one of three input levels (v il , v ih or v ihh ). ( note 6 ) v ss ?v dd + 8.0v vv dd < 4.5v v dd start voltage to ensure wiper reset v bor ? ? 1.65 v ram retention voltage (v ram ) < v bor v dd rise rate to ensure power-on reset v ddrr ( note 9 )v/ms delay after device exits the reset state (v dd > v bor ) t bord ?1020s note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
? 2008 microchip technology inc. ds22091a-page 5 mcp454x/456x/464x/466x supply current (note 10) i dd ? ? 950 a serial interface active, hvc/a0 = v ih (or v il ) write all 0?s to volatile wiper 0 v dd = 5.5v, f scl = 3.4 mhz ? ? 725 a serial interface active, hvc/a0 = v ih (or v il ) write all 0?s to volatile wiper 0 v dd = 5.5v, f scl = 100 khz ? ? 575 a ee write current (write cycle) (non-volatile device only), v dd = 5.5v, f scl = 400 khz, write all 0?s to nonvolatile wiper 0 scl = v il or v ih ? 2.5 5 a serial interface inactive, (stop condition, scl = sda = v ih ), wiper = 0 v dd = 5.5v, hvc/a0 = v ih ? 150 300 a serial interface active, hvc/a0 = v ihh decrement volatile wiper 0 v dd = 5.5v, f scl = 400 khz ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
mcp454x/456x/464x/466x ds22091a-page 6 ? 2008 microchip technology inc. resistance ( 20%) r ab 4.0 5 6.0 k -502 devices (note 1) 8.0 10 12.0 k -103 devices (note 1) 40.0 50 60.0 k -503 devices (note 1) 80.0 100 120.0 k -104 devices (note 1) resolution n 257 taps 8-bit no missing codes 129 taps 7-bit no missing codes step resistance r s ?r ab / (256) ? 8-bit note 6 ?r ab / (128) ? 7-bit note 6 nominal resistance match |r ab0 - r ab1 | / r ab ? 0.2 1.25 % mcp46x1 devices only |r bw0 - r bw1 | / r bw ? 0.25 1.5 % mcp46x2 devices only, code = full-scale wiper resistance ( note 3, note 4) r w ?75160 v dd = 5.5 v, i w = 2.0 ma, code = 00h ?75300 v dd = 2.7 v, i w = 2.0 ma, code = 00h nominal resistance te m p c o r ab / t ? 50 ? ppm/c t a = -20c to +70c ? 100 ? ppm/c t a = -40c to +85c ? 150 ? ppm/c t a = -40c to +125c ratiometeric te m p c o v wb / t ? 15 ? ppm/c code = midscale (80h or 40h) resistor terminal input voltage range (terminals a, b and w) v a, v w, v b vss ? v dd v note 5, note 6 ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
? 2008 microchip technology inc. ds22091a-page 7 mcp454x/456x/464x/466x maximum current through terminal (a, w or b) note 6 i t ? ? 2.5 ma terminal a i aw , w = full-scale (fs) ? ? 2.5 ma terminal b i bw , w = zero scale (zs) ? ? 2.5 ma terminal w i aw or i bw , w = fs or zs ? ? 1.38 ma terminal a and terminal b i ab , v b = 0v, v a = 5.5v, r ab(min) = 4000 ? ? 0.688 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 8000 ? ? 0.138 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 40000 ? ? 0.069 ma i ab , v b = 0v, v a = 5.5v, r ab(min) = 80000 leakage current into a, w or b i wl ? 100 ? na mcp4xx1 pxa = pxw = pxb = v ss ? 100 ? na mcp4xx2 pxb = pxw = v ss ? 100 ? na terminals disconnected (r1hw = r0hw = 0) ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
mcp454x/456x/464x/466x ds22091a-page 8 ? 2008 microchip technology inc. full-scale error ( mcp4xx1 only) (8-bit code = 100h, 7-bit code = 80h) v wfse -6.0 -0.1 ? lsb 5 k 8-bit 3.0v v dd 5.5v -4.0 -0.1 ? lsb 7-bit 3.0v v dd 5.5v -3.5 -0.1 ? lsb 10 k 8-bit 3.0v v dd 5.5v -2.0 -0.1 ? lsb 7-bit 3.0v v dd 5.5v -0.8 -0.1 ? lsb 50 k 8-bit 3.0v v dd 5.5v -0.5 -0.1 ? lsb 7-bit 3.0v v dd 5.5v -0.5 -0.1 ? lsb 100 k 8-bit 3.0v v dd 5.5v -0.5 -0.1 ? lsb 7-bit 3.0v v dd 5.5v zero-scale error ( mcp4xx1 only) (8-bit code = 00h, 7-bit code = 00h) v wzse ?+0.1+6.0lsb5k 8-bit 3.0v v dd 5.5v ? +0.1 +3.0 lsb 7-bit 3.0v v dd 5.5v ? +0.1 +3.5 lsb 10 k 8-bit 3.0v v dd 5.5v ? +0.1 +2.0 lsb 7-bit 3.0v v dd 5.5v ? +0.1 +0.8 lsb 50 k 8-bit 3.0v v dd 5.5v ? +0.1 +0.5 lsb 7-bit 3.0v v dd 5.5v ? +0.1 +0.5 lsb 100 k 8-bit 3.0v v dd 5.5v ? +0.1 +0.5 lsb 7-bit 3.0v v dd 5.5v potentiometer integral non-linearity inl -1 0.5 +1 lsb 8-bit 3.0v v dd 5.5v mcp4xx1 devices only (note 2) -0.5 0.25 +0.5 lsb 7-bit potentiometer differential non-linearity dnl -0.5 0.25 +0.5 lsb 8-bit 3.0v v dd 5.5v mcp4xx1 devices only (note 2) -0.25 0.125 +0.25 lsb 7-bit bandwidth -3 db (see figure 2-58 , load = 30 pf) bw ? 2 ? mhz 5 k 8-bit code = 80h ? 2 ? mhz 7-bit code = 40h ?1?mhz10k 8-bit code = 80h ? 1 ? mhz 7-bit code = 40h ? 200 ? khz 50 k 8-bit code = 80h ? 200 ? khz 7-bit code = 40h ? 100 ? khz 100 k 8-bit code = 80h ? 100 ? khz 7-bit code = 40h ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
? 2008 microchip technology inc. ds22091a-page 9 mcp454x/456x/464x/466x rheostat integral non-linearity mcp45x1 ( note 4, note 8 ) mcp4xx2 devices only (note 4) r-inl -1.5 0.5 +1.5 lsb 5 k 8-bit 5.5v, i w = 900 a -8.25 +4.5 +8.25 lsb 3.0v, i w = 480 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 900 a -6.0 +4.5 +6.0 lsb 3.0v, i w = 480 a ( note 7 ) -1.5 0.5 +1.5 lsb 10 k 8-bit 5.5v, i w = 450 a -5.5 +2.5 +5.5 lsb 3.0v, i w = 240 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 450 a -4.0 +2.5 +4.0 lsb 3.0v, i w = 240 a ( note 7 ) -1.5 0.5 +1.5 lsb 50 k 8-bit 5.5v, i w = 90 a -2.0 +1 +2.0 lsb 3.0v, i w = 48 a ( note 7 ) -1.125 0.5 +1.125 lsb 7-bit 5.5v, i w = 90 a -1.5 +1 +1.5 lsb 3.0v, i w = 48 a ( note 7 ) -1.0 0.5 +1.0 lsb 100 k 8-bit 5.5v, i w = 45 a -1.5 +0.25 +1.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.8 0.5 +0.8 lsb 7-bit 5.5v, i w = 45 a -1.125 +0.25 +1.125 lsb 3.0v, i w = 24 a ( note 7 ) ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
mcp454x/456x/464x/466x ds22091a-page 10 ? 2008 microchip technology inc. rheostat differential non-linearity mcp45x1 ( note 4, note 8 ) mcp4xx2 devices only (note 4) r-dnl -0.5 0.25 +0.5 lsb 5 k 8-bit 5.5v, i w = 900 a -1.0 +0.5 +1.0 lsb 3.0v, i w = 480 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 900 a -0.75 +0.5 +0.75 lsb 3.0v, i w = 480 a ( note 7 ) -0.5 0.25 +0.5 lsb 10 k 8-bit 5.5v, i w = 450 a -1.0 +0.25 +1.0 lsb 3.0v, i w = 240 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 450 a -0.75 +0.5 +0.75 lsb 3.0v, i w = 240 a ( note 7 ) -0.5 0.25 +0.5 lsb 50 k 8-bit 5.5v, i w = 90 a -0.5 0.25 +0.5 lsb 3.0v, i w = 48 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 90 a -0.375 0.25 +0.375 lsb 3.0v, i w = 48 a ( note 7 ) -0.5 0.25 +0.5 lsb 100 k 8-bit 5.5v, i w = 45 a -0.5 0.25 +0.5 lsb 3.0v, i w = 24 a ( note 7 ) -0.375 0.25 +0.375 lsb 7-bit 5.5v, i w = 45 a -0.375 0.25 +0.375 lsb 3.0v, i w = 24 a ( note 7 ) capacitance (p a )c aw ? 75 ? pf f =1 mhz, code = full-scale capacitance (p w )c w ? 120 ? pf f =1 mhz, code = full-scale capacitance (p b )c bw ? 75 ? pf f =1 mhz, code = full-scale ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
? 2008 microchip technology inc. ds22091a-page 11 mcp454x/456x/464x/466x digital inputs/outputs (sda, sck, hvc/a0, a1, a2, wp ) schmitt trigger high input threshold v ih 0.45 v dd ?? vall inputs except sda and scl 2.7v v dd 5.5v (allows 2.7v digital v dd with 5v analog v dd ) 0.5 v dd ?? v 1.8v v dd 2.7v 0.7 v dd ?v max v sda and scl 100 khz 0.7 v dd ?v max v400khz 0.7 v dd ?v max v1.7mhz 0.7 v dd ?v max v3.4mhz schmitt trigger low input threshold v il ? ? 0.2v dd v all inputs except sda and scl -0.5 ? 0.3v dd v sda and scl 100 khz -0.5 ? 0.3v dd v400khz -0.5 ? 0.3v dd v1.7mhz -0.5 ? 0.3v dd v3.4mhz hysteresis of schmitt trigger inputs (note 6) v hys ?0.1v dd ? v all inputs except sda and scl n.a. ? ? v sda and scl 100 khz v dd < 2.0v n.a. ? ? v v dd 2.0v 0.1 v dd ?? v 400 khz v dd < 2.0v 0.05 v dd ?? v v dd 2.0v 0.1 v dd ?? v 1.7mhz 0.1 v dd ?? v 3.4mhz high voltage input entry voltage v ihhen 8.5 ? 12.5 (6) v threshold for wiperlock? technology high voltage input exit voltage v ihhex ??v dd + 0.8v (6) v high voltage limit v max ??12.5 (6) v pin can tolerate v max or less. output low voltage (sda) v ol v ss ?0.2v dd vv dd < 2.0v, i ol = 1 ma v ss ?0.4 vv dd 2.0v, i ol = 3 ma ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
mcp454x/456x/464x/466x ds22091a-page 12 ? 2008 microchip technology inc. weak pull-up / pull-down current i pu ? ? 1.75 ma internal v dd pull-up, v ihh pull-down v dd = 5.5v, v ihh = 12.5v ? 170 ? a hvc pin, v dd = 5.5v, v hvc = 3v hvc pull-up / pull-down resistance r hvc ?16?k v dd = 5.5v, v hvc = 3v input leakage cur- rent i il -1 ? 1 a v in = v dd and v in = v ss pin capacitance c in , c out ?10?pff c = 3.4 mhz ram (wiper) value value range n 0h ? 1ffh hex 8-bit device 0h ? 1ffh hex 7-bit device tcon por/bor value n tcon 1ffh hex all terminals connected eeprom endurance e ndurance ? 1m ? cycles eeprom range n 0h ? 1ffh hex initial factory setting n 80h hex 8-bit wiperlock technology = off 40h hex 7-bit wiperlock technology = off eeprom pro- gramming write cycle time t wc ?510ms power requirements power supply sensitivity ( mcp45x2 and mcp46x2 only) pss ? 0.0015 0.0035 %/% 8-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 80h ? 0.0015 0.0035 %/% 7-bit v dd = 2.7v to 5.5v, v a = 2.7v, code = 40h ac/dc characteristi cs (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c t a +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to 5.5v, 5 k , 10 k , 50 k , 100 k devices. typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between terminal a to terminal b. 2: inl and dnl are measured at v w with v a = v dd and v b = v ss . 3: mcp4xx1 only. 4: mcp4xx2 only, includes v wzse and v wfse . 5: resistor terminals a, w and b?s polarity with respect to each other is not restricted. 6: this specification by design. 7: non-linearity is affected by wiper resistance (r w ), which changes signif icantly overvoltage and temperature. 8: the mcp4xx1 is externally connected to match the configurations of the mcp45x2 and mcp46x2 , and then tested. 9: por/bor is not rate dependent. 10: supply current is independent of current through the resistor network
? 2008 microchip technology inc. ds22091a-page 13 mcp454x/456x/464x/466x figure 1-1: i 2 c bus start/stop bits timing waveforms. table 1-1: i 2 c bus start/stop bits requirements i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. symbol characteristic min max units conditions f scl standard mode 0 100 khz c b = 400 pf, 1.8v - 5.5v fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v high-speed 1.7 0 1.7 mhz c b = 400 pf, 4.5v - 5.5v high-speed 3.4 0 3.4 mhz c b = 100 pf, 4.5v - 5.5v d102 cb bus capacitive loading 100 khz mode ? 400 pf 400 khz mode ? 400 pf 1.7 mhz mode ? 400 pf 3.4 mhz mode ? 100 pf 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period the first clock pulse is generated hold time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 92 t su : sto stop condition 100 khz mode 4000 ? ns setup time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ns 1.7 mhz mode 160 ? ns 3.4 mhz mode 160 ? ns 91 93 scl sda start condition stop condition 90 92
mcp454x/456x/464x/466x ds22091a-page 14 ? 2008 microchip technology inc. figure 1-2: i 2 c bus data timing. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out table 1-2: i 2 c bus data requirements (slave mode) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4000 ? ns 1.8v-5.5v 400 khz mode 600 ? ns 2.7v-5.5v 1.7 mhz mode 120 ns 4.5v-5.5v 3.4 mhz mode 60 ? ns 4.5v-5.5v 101 t low clock low time 100 khz mode 4700 ? ns 1.8v-5.5v 400 khz mode 1300 ? ns 2.7v-5.5v 1.7 mhz mode 320 ns 4.5v-5.5v 3.4 mhz mode 160 ? ns 4.5v-5.5v note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp46x1/mcp46x2 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this s pecification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications fo r the receiving device. 4: use cb in pf for the calculations. 5: not tested 6: a master transmitter must provide a delay to ensur e that difference between sda and scl fall times do not unintentionally create a start or stop condition. 7: ensured by the t aa 3.4 mhz specification test.
? 2008 microchip technology inc. ds22091a-page 15 mcp454x/456x/464x/466x 102a (5) t rscl scl rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf (100 pf maxi- mum for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 1.7 mhz mode 20 160 ns after a repeated start con- dition or an acknowledge bit 3.4 mhz mode 10 40 ns 3.4 mhz mode 10 80 ns after a repeated start condition or an acknowl- edge bit 102b (5) t rsda sda rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 103a (5) t fscl scl fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb 300 ns 1.7 mhz mode 20 80 ns 3.4 mhz mode 10 40 ns 103b (5) t fsda sda fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf (100 pf max for 3.4 mhz mode) 400 khz mode 20 + 0.1cb (4) 300 ns 1.7 mhz mode 20 160 ns 3.4 mhz mode 10 80 ns 106 t hd:dat data input hold time 100 khz mode 0 ? ns 1.8v-5.5v, note 6 400 khz mode 0 ? ns 2.7v-5.5v, note 6 1.7 mhz mode 0 ? ns 4.5v-5.5v, note 6 3.4 mhz mode 0 ? ns 4.5v-5.5v, note 6 table 1-2: i 2 c bus data requirements (slave mode) (continued) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a dev ice does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp46x1/mcp46x2 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this s pecification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications fo r the receiving device. 4: use cb in pf for the calculations. 5: not tested 6: a master transmitter must provide a delay to ensur e that difference between sda and scl fall times do not unintentionally create a start or stop condition. 7: ensured by the t aa 3.4 mhz specification test.
mcp454x/456x/464x/466x ds22091a-page 16 ? 2008 microchip technology inc. 107 t su:dat data input setup time 100 khz mode 250 ? ns note 2 400 khz mode 100 ? ns 1.7 mhz mode 10 ? ns 3.4 mhz mode 10 ? ns 109 t aa output valid from clock 100 khz mode ? 3450 ns note 1 400 khz mode ? 900 ns 1.7 mhz mode ? 150 ns cb = 100 pf, note 1 , note 7 ? 310 ns cb = 400 pf, note 1 , note 5 3.4 mhz mode ? 150 ns cb = 100 pf, note 1 110 t buf bus free time 100 khz mode 4700 ? ns time the bus must be free before a new transmission can start 400 khz mode 1300 ? ns 1.7 mhz mode n.a. ? ns 3.4 mhz mode n.a. ? ns t sp input filter spike suppression (sda and scl) 100 khz mode ? 50 ns philips spec states n.a. 400 khz mode ? 50 ns 1.7 mhz mode ? 10 ns spike suppression 3.4 mhz mode ? 10 ns spike suppression table 1-2: i 2 c bus data requirements (slave mode) (continued) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 c t a +125 c (extended) operating voltage v dd range is described in ac/dc characteristics param. no. sym characteristic min max units conditions note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp46x1/mcp46x2 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this s pecification is not a part of the i 2 c specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications fo r the receiving device. 4: use cb in pf for the calculations. 5: not tested 6: a master transmitter must provide a delay to ensur e that difference between sda and scl fall times do not unintentionally create a start or stop condition. 7: ensured by the t aa 3.4 mhz specification test.
? 2008 microchip technology inc. ds22091a-page 17 mcp454x/456x/464x/466x temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss =gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 8l-soic ja ? 145.5 ? c/w thermal resistance, 8l-msop ja ?211?c/w thermal resistance, 8l-dfn (3x3) ja ?60?c/w thermal resistance, 10l-msop ja ?202?c/w thermal resistance, 14l-soic ja ? 95.3 ? c/w thermal resistance, 14l-msop ja ?n/a?c/w thermal resistance, 16l-qfn ja ?47?c/w
mcp454x/456x/464x/466x ds22091a-page 18 ? 2008 microchip technology inc. 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-1: device current (i dd ) vs. i 2 c frequency (f scl ) and ambient temperature (v dd = 2.7v and 5.5v). figure 2-2: device current (i shdn ) and v dd . (hvc = v dd ) vs. ambient temperature. figure 2-3: write current (i write ) vs. ambient temperature. figure 2-4: hvc pull-up/pull-down resistance (r hvc ) and current (i hvc ) vs. hvc input voltage (v hvc ) (v dd = 5.5v). figure 2-5: hvc high input entry/exit threshold vs. ambient temperature and v dd . note: the graphs and tables provided following this note ar e a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 100 200 300 400 500 600 700 800 -40 0 40 80 120 temperature (c) i dd (ua) 100 khz, 5.5v 400 khz, 5.5v 1.7 mhz, 5.5v 3.4 mhz, 5.5v 100 khz, 2.7v 400 khz, 2.7v 1.7 mhz, 2.7v 3.4 mhz, 2.7v 0.5 1 1.5 2 2.5 3 -40 0 40 80 120 temperature (c) istandby (ua) 5.5v 2.7v 300 320 340 360 380 400 420 -40 0 40 80 120 temperature (c) i write (a) 5.5v 0 50 100 150 200 250 2345678910 v hvc (v) r hvc (kohms) -1000 -800 -600 -400 -200 0 200 400 600 800 1000 i hvc (a) i hvc r hvc 0 2 4 6 8 10 12 -40 -20 0 20 40 60 80 100 120 ambient temperature (c) hvc v pp threshold (v) 2.7v exit 5.5v exit 2.7v entry 5.5v entry
? 2008 microchip technology inc. ds22091a-page 19 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-6: 5k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-7: 5k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-8: 5k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-9: 5k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl -40c 25c 85c r w 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 0 2 4 6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1.25 -0.75 -0.25 0.25 0.75 1.25 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
mcp454x/456x/464x/466x ds22091a-page 20 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-10: 5k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-11: 5k ? r wb ( ) vs. wiper setting and ambient temperature. 5050 5100 5150 5200 5250 5300 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 0 1000 2000 3000 4000 5000 6000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
? 2008 microchip technology inc. ds22091a-page 21 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-12: 5k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-13: 5k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-14: 5k ? power-up wiper response time (20 ms/div). figure 2-15: 5k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). figure 2-16: 5k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div).
mcp454x/456x/464x/466x ds22091a-page 22 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-17: 10 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-18: 10 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-19: 10 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-20: 10 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.5 0 0.5 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 25 50 75 100 125 150 175 200 225 250 wiper setting (decimal) wiper resistance (r w ) (ohms) -2 -1 0 1 2 3 4 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
? 2008 microchip technology inc. ds22091a-page 23 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-21: 10 k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-22: 10 k ? r wb ( ) vs. wiper setting and ambient temperature. 9850 9900 9950 10000 10050 10100 10150 10200 10250 10300 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 2000 4000 6000 8000 10000 12000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
mcp454x/456x/464x/466x ds22091a-page 24 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-23: 10 k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-24: 10 k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-25: 10 k ? power-up wiper response time (1 s/div). figure 2-26: 10 k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). figure 2-27: 10 k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div).
? 2008 microchip technology inc. ds22091a-page 25 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-28: 50 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-29: 50 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-30: 50 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-31: 50 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
mcp454x/456x/464x/466x ds22091a-page 26 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-32: 50 k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-33: 50 k ? r wb ( ) vs. wiper setting and ambient temperature. 49000 49500 50000 50500 51000 51500 52000 52500 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 1.8v 5.5v 0 10000 20000 30000 40000 50000 60000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) r wb (ohms) -40c 25c 85c 125c
? 2008 microchip technology inc. ds22091a-page 27 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-34: 50 k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-35: 50 k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-36: 50 k ? power-up wiper response time (1 s/div). figure 2-37: 50 k ? low-voltage increment wiper settling time (v dd = 5.5v) (1 s/div). figure 2-38: 50 k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div).
mcp454x/456x/464x/466x ds22091a-page 28 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-39: 100 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-40: 100 k pot mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). figure 2-41: 100 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 5.5v). figure 2-42: 100 k rheo mode ? r w ( ), inl (lsb), dnl (lsb) vs. wiper setting and ambient temperature (v dd = 3.0v). 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.1 0 0.1 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (r w ) (ohms) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c 20 60 100 140 180 220 260 300 0 32 64 96 128 160 192 224 256 wiper setting (decimal) wiper resistance (rw) (ohms) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 error (lsb) -40c rw 25c rw 85c rw 125c rw -40c inl 25c inl 85c inl 125c inl -40c dnl 25c dnl 85c dnl 125c dnl inl dnl r w -40c 25c 85c 125c
? 2008 microchip technology inc. ds22091a-page 29 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-43: 100 k ? nominal resistance ( ) vs. ambient temperature and v dd . figure 2-44: 100 k ? r wb ( ) vs. wiper setting and ambient temperature. 98500 99000 99500 100000 100500 101000 101500 102000 102500 103000 103500 -40 0 40 80 120 ambient temperature (c) nominal resistance (r ab ) (ohms) 2.7v 5.5v 1.8v 0 20000 40000 60000 80000 100000 120000 0 32 64 96 128 160 192 224 256 wiper setting (decimal) rwb (ohms) -40c 25c 85c 125c
mcp454x/456x/464x/466x ds22091a-page 30 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-45: 100 k ? low-voltage decrement wiper settling time (v dd = 5.5v) (1 s/div). figure 2-46: 100 k ? low-voltage decrement wiper settling time (v dd = 2.7v) (1 s/div). figure 2-47: 100 k ? low-voltage increment wiper settling time (v dd =5.5v) (1 s/div). figure 2-48: 100 k ? low-voltage increment wiper settling time (v dd = 2.7v) (1 s/div)
? 2008 microchip technology inc. ds22091a-page 31 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-49: resistor network 0 to resistor network 1 r ab (5 k ) mismatch vs. v dd and temperature. figure 2-50: resistor network 0 to resistor network 1 r ab (10 k ) mismatch vs. v dd and temperature. figure 2-51: resistor network 0 to resistor network 1 r ab (50 k ) mismatch vs. v dd and temperature. figure 2-52: resistor network 0 to resistor network 1 r ab (100 k ) mismatch vs. v dd and temperature. 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -40 0 40 80 120 temperature (c) % 5.5v 3.0v -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -40 0 40 80 120 temperature (c) % 5.5v 3.0v 0 0.02 0.04 0.06 0.08 0.1 0.12 -40 0 40 80 120 temperature (c) % 5.5v 3.0v -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -40 10 60 110 temperature (c) % 5.5v 3.0v
mcp454x/456x/464x/466x ds22091a-page 32 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-53: v ih (sda, scl) vs. v dd and temperature. figure 2-54: v il (sda, scl) vs. v dd and temperature. figure 2-55: v ol (sda) vs. v dd and temperature (i ol = 3 ma). 1 1.5 2 2.5 3 3.5 4 -40 0 40 80 120 temperature (c) v ih (v) 5.5v 2.7v 1 1.5 2 -40 0 40 80 120 temperature (c) v il (v) 5.5v 2.7v 50 70 90 110 130 150 170 190 210 230 -40 0 40 80 120 temperature (c) v ol (mv) 5.5v 2.7v
? 2008 microchip technology inc. ds22091a-page 33 mcp454x/456x/464x/466x note: unless otherwise indicated, t a = +25c, v dd = 5v, v ss = 0v. figure 2-56: nominal eeprom write cycle time vs. v dd and temperature. figure 2-57: por/bor trip point vs. v dd and temperature. 2.1 test circuits figure 2-58: -3 db gain vs. frequency test. 3.0 3.2 3.4 3.6 3.8 4.0 4.2 -40 0 40 80 120 temperature (c) t wc (ms) 0 0.2 0.4 0.6 0.8 1 1.2 -40 0 40 80 120 temperature (c) v dd (v) 2.7v 5.5v + - v out 2.5v dc +5v a b w offset gnd v in
mcp454x/456x/464x/466x ds22091a-page 34 ? 2008 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in ta b l e 3 - 1 . additional descriptions of the device pins follows. table 3-1: pinout description fo r the mcp454x/456x/464x/466x pin weak pull-up/ down (1) standard function single dual symbol i/o buffer type rheo pot (1) rheo pot 8l 8l 10l 14l 16l 1 1 1 1 16 hvc/a0 i hv w/st ?smart? high voltage command / address 0. 2 2 2 2 1 scl i hv w/st yes i 2 c clock input. 3 3 3 3 2 sda i/o hv w/st yes i 2 c serial data i/o. open drain output 44443, 4 v ss ? p ? ground ? ? 5 5 5 p1b a analog no potentiometer 1 terminal b ? ? 6 6 6 p1w a analog no potentiometer 1 wiper terminal ? ? ? 7 7 p1a a analog no potentiometer 1 terminal a ? 5 ? 8 8 p0a a analog no potentiometer 0 terminal a 5 6 7 9 9 p0w a analog no potentiometer 0 wiper terminal 6 7 8 10 10 p0b a analog no potentiometer 0 terminal b ???1112 wp i hv w/st ?smart? hardware eeprom write protect ? ? ? 12 13 a2 i hv w/st ?smart? address 2 7 ? 9 13 14 a1 i hv w/st ?smart? address 1 8 8 10 14 15 v dd ? p ? positive power supply input ? ? ? ? 11 nc ? ? ? no connection (2) (2) (2) ? (2) exposed pad ? ? ? note 2 legend: hv w/st = high voltage tolerant input (with schmidtt trigger input) a = analog pins (potentiometer terminals) i = digital input (high z) o = digital output i/o = input / output p = power note 1: the pin?s ?smart? pull-up shuts off while the pin is forced low. this is done to reduce the standby and shut- down current. 2: the dfn and qfn packages have a contact on the bottom of the package. this contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device?s v ss pin.
? 2008 microchip technology inc. ds22091a-page 35 mcp454x/456x/464x/466x 3.1 high voltage command / address 0 (hvc/a0) the hvc/a0 pin is the address 0 input for the i 2 c interface as well as the hig h voltage command pin. at the device?s por/bor the value of the a0 address bit is latched. this input along with the a2 and a1 pins completes the device address. this allows up to 8 mcp45xx/46xx devices can be on a single i 2 c bus. during normal operation the the voltage on this pin determines if the i 2 c command is a normal command or a high voltage command (when hvc/a0 = v ihh ). 3.2 serial clock (scl) the scl pin is the serial interfaces serial clock pin. this pin is connected to the host controllers scl pin. the mcp45xx/46xx is a slave device, so it?s scl pin accepts only external clock signals. the scl pin has an internal pull-up resistor to the device?s v dd . 3.3 serial data (sda) the sda pin is the serial interfaces serial data pin. this pin is connected to t he host controllers sda pin. the sda pin is an open-drain n-channel driver with an internal pull-up resistor to the device?s v dd . 3.4 ground (v ss ) the v ss pin is the device ground reference. 3.5 potentiometer terminal b the terminal b pin is connected to the internal potentiometer?s terminal b. the potentiometer?s terminal b is the fixed connection to the zero scale wiper value of the digital potentiome- ter. this corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. the terminal b pin does not have a polarity relative to the terminal w or a pins. the terminal b pin can support both positive and negative current. the voltage on terminal b must be between v ss and v dd . mcp46xx devices have two terminal b pins, one for each resistor network. 3.6 potentiometer wiper (w) terminal the terminal w pin is connected to the internal potenti- ometer?s terminal w (the wiper). the wiper terminal is the adjustable terminal of the digital potentiometer. the terminal w pin does not have a polarity relative to terminals a or b pins. the terminal w pin can support both positive and negative current. the voltage on terminal w must be between v ss and v dd . mcp46xx devices have two terminal w pins, one for each resistor network. 3.7 potentiometer terminal a the terminal a pin is available on the mcp4xx1 devices, and is connected to the internal potentiome- ter?s terminal a. the potentiometer?s terminal a is the fixed connection to the full-scale wiper value of the digital potentiome- ter. this corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. the terminal a pin does not have a polarity relative to the terminal w or b pins. the terminal a pin can support both positive and negative current. the voltage on terminal a must be between v ss and v dd . the terminal a pin is not available on the mcp4xx2 devices, and the internally terminal a signal is floating. mcp46x1 devices have two terminal a pins, one for each resistor network. 3.8 write protect (wp ) the wp pin is used to force the non-volatile memory to be write protected. 3.9 address 2 (a2) the a2 pin is the i 2 c interface?s address 2 pin. along with the a1 and a0 pins, up to 8 mcp45xx/46xx devices can be on a single i 2 c bus. 3.10 address 1 (a1) the a2 pin is the i 2 c interface?s address 1 pin. along with the a2 and a0 pins, up to 8 mcp45xx/46xx devices can be on a single i 2 c bus. 3.11 positive power supply input (v dd ) the v dd pin is the device?s positive power supply input. the input power supply is relative to v ss . while the device v dd < v min (2.7v), the electrical performance of the device may not meet the data sheet specifications.
mcp454x/456x/464x/466x ds22091a-page 36 ? 2008 microchip technology inc. 4.0 functional overview this data sheet covers a family of thirty-two digital potentiometer and rheost at devices that will be referred to as mcp4xxx. the mcp4xx1 devices are the potentiometer configuration, while the mcp4xx2 devices are the rheostat configuration. as the device block diagram shows, there are four main functional blocks. these are: ? por/bor operation ? memory map ? resistor network ? serial interface (i 2 c) the por/bor operation an d the memory map are discussed in this section and the resistor network and i 2 c operation are described in their own sections. the device commands commands are discussed in section 7.0 . 4.1 por/bor operation the power-on reset is the case where the device is having power applied to it starting from the v ss level. the brown-out reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. the devices ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). the maximum v por /v bor voltage is less than 1.8v. when v por /v bor < v dd < 2.7v, the electrical performance may not meet the data sheet specifications. in this region, the device is capable of reading and writing to its eeprom and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. 4.1.1 power-on reset when the device powers up, the device v dd will cross the v por /v bor voltage. once the v dd voltage crosses the v por /v bor voltage the following happens: ? volatile wiper register is loaded with value in the corresponding non-volatile wiper register ? the tcon register is loaded it?s default value ? the device is capable of digital operation 4.1.2 brown-out reset when the device powers down, the device v dd will cross the v por /v bor voltage. once the v dd voltage decreases below the v por /v bor voltage the following happens: ? serial interface is disabled ? eeprom writes are disabled if the v dd voltage decreases below the v ram voltage the following happens: ? volatile wiper registers may become corrupted ? tcon register may become corrupted as the voltage recovers above the v por /v bor voltage see section 4.1.1 ?power-on reset? . serial commands not completed due to a brown-out condition may cause the memory location (volatile and non-volatile) to become corrupted. 4.2 memory map the device memory is 16 locations that are 9-bits wide (16x9 bits). this memory space contains both volatile and non-volatile locations (see table 4-1 ). table 4-1: memory map address function memory type 00h volatile wiper 0 ram 01h volatile wiper 1 ram 02h non-volatile wiper 0 eeprom 03h non-volatile wiper 1 eeprom 04h volatile tcon register ram 05h status register ram 06h data eeprom eeprom 07h data eeprom eeprom 08h data eeprom eeprom 09h data eeprom eeprom 0ah data eeprom eeprom 0bh data eeprom eeprom 0ch data eeprom eeprom 0dh data eeprom eeprom 0eh data eeprom eeprom 0fh data eeprom eeprom
? 2008 microchip technology inc. ds22091a-page 37 mcp454x/456x/464x/466x 4.2.1 non-volatile memory (eeprom) this memory can be grouped into two uses of non-vol- atile memory. these are: ? general purpose registers ? non-volatile wiper registers the non-volatile wipers starts functioning below the devices v por /v bor trip point. 4.2.1.1 general purpose registers these locations allow the user to store up to 10 (9-bit) locations worth of information. 4.2.1.2 non-volatile wiper registers these locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a por/bor event. there are up to two registers, one for each resistor network. the non-volatile wiper register enables stand-alone operation of the device (wit hout microcontroller control) after being programmed to the desired value. 4.2.1.3 factory initializ ation of non-volatile memory (eeprom) the non-volatile wiper values will be initialized to mid-scale value. this is shown in table 4-2 . the general purpose eeprom memory will be programmed to a default value of 0xff. it is good practice in the manufacturing flow to configure the device to your desired settings. table 4-2: default factory settings selection 4.2.1.4 special features there are 3 non-volatile bits that are not directly mapped into the address space. these bits control the following functions: ? eeprom write protect ? wiperlock technology for non-volatile wiper 0 ? wiperlock technology for non-volatile wiper 1 the operation of wiperlock technology is discussed in section 5.3 . the state of the wl0, wl1, and wp bits is reflected in the status register (see register 4-1 ). eeprom write protect all internal eeprom memory can be write protected. when eeprom memory is write protected, write commands to the internal eeprom are prevented. write protect (wp ) can be enabled/disabled by two methods. these are: ? external wp hardware pin (mcp46x1 devices only) ? non-volatile configuration bit high voltage commands are required to enable and disable the nonvolatile wp bit. these commands are shown in section 7.8 ?modify write protect or wip- erlock technology (high voltage)? . to write to eeprom, both the external wp pin and the internal wp eeprom bit mu st be disabled. write protect does not block commands to the volatile registers. 4.2.2 volatile memory (ram) there are four volatile memory locations. these are: ? volatile wiper 0 ? volatile wiper 1 (dual resistor network devices only) ? status register ? terminal control (tcon) register the volatile memory starts functioning at the ram retention voltage (v ram ). resistance code typical r ab value default por wiper setting wiper code wiperlock? technology and write protect setting 8-bit 7-bit -502 5.0 k mid-scale 80h 40h disabled -103 10.0 k mid-scale 80h 40h disabled -503 50.0 k mid-scale 80h 40h disabled -104 100.0 k mid-scale 80h 40h disabled
mcp454x/456x/464x/466x ds22091a-page 38 ? 2008 microchip technology inc. 4.2.2.1 status (status) register this register contains 4 status bits. these bits show the state of the wiperlock bits, the write protect bit, and if an eeprom write cycle is active. the status register can be accessed via the read commands. register 4-1 describes each status register bit. the status register is placed at address 05h. register 4-1: status register (address = 0x05) r-1 r-1 r-1 r-1 r-1 r-0 r-x r-x r-x d8:d4 eewa wl1 (1) wl0 (1) wp (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 8-4 d8:d4: reserved. forced to ?1? bit 3 eewa: eeprom write active status bit this bit indicates if the eeprom write cycle is occurring. 1 = an eeprom write cycle is currently occurring. only serial commands to the volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = an eeprom write cycle is not currently occurring bit 2 wl1: wiperlock status bit for resistor network 1 (refer to section 5.3 ?wiperlock? technology? for further information) wiperlock (wl) prevents the volatile and non-volatile wiper 1 addresses and the tcon register bits r1hw, r1a, r1w, and r1b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon register bits r1hw, r1a, r1w, and r1b of resistor network 1 (pot 1) are ?locked? (write protected) 0 = wiper and tcon of resistor network 1 (pot 1) can be modified note: the wl1 bit always reflects the result of the last programming cycle to the non-volatile wl1 bit. after a por or bor event, the wl1 bit is loaded with the non-volatile wl1 bit value. bit 1 wl0: wiperlock status bit for resistor network 0 (refer to section 5.3 ?wiperlock? technology? for further information) the wiperlock technology bits (wlx) prevents the volatile and non-volatile wiper 0 addresses and the tcon register bits r0hw, r0a, r0w, and r0 b from being written to. high voltage commands are required to enable and disable wiperlock technology. 1 = wiper and tcon register bits r0hw, r0a, r0w, and r0b of resistor network 0 (pot 0) are ?locked? (write protected) 0 = wiper and tcon of resistor network 0 (pot 0) can be modified note: the wl0 bit always reflects the result of the last programming cycle to the non-volatile wl0 bit. after a por or bor event, the wl0 bit is loaded with the non-volatile wl0 bit value. note 1: requires a high voltage command to modify the state of th is bit (for non-volatile devices only). this bit is not directly written, but reflects the system state (for this feature).
? 2008 microchip technology inc. ds22091a-page 39 mcp454x/456x/464x/466x bit 0 wp: eeprom write protect status bit (refer to section ?eeprom write protect? for further infor- mation) this bit indicates the status of the write protection on the eeprom memory. when write protect is enabled, writes to all non-volati le memory are prevented. this includes the gener al purpose eeprom memory, and the non-volatile wiper registers. write protect does not block modification of the volatile wiper register values or the volatile tcon re gister value (via increm ent, decrement, or write commands). this status bit is an or of the devices write protect pin (wp ) and the internal non-volatile wp bit. high voltage commands are require d to enable a nd disable the internal wp eeprom bit. 1 = eeprom memory is write protected 0 = eeprom memory can be written register 4-1: status register (address = 0x05) (continued) note 1: requires a high voltage command to modify the state of th is bit (for non-volatile devices only). this bit is not directly written, but reflects the system state (for this feature).
mcp454x/456x/464x/466x ds22091a-page 40 ? 2008 microchip technology inc. 4.2.2.2 terminal contro l (tcon) register this register contains 8 control bits. four bits are for wiper 0, and four bits are for wiper 1. register 4-2 describes each bit of the tcon register. the state of each resistor network terminal connection is individually controlled. that is, each terminal connection (a, b and w) can be individually connected/ disconnected from the resistor network. this allows the system to minimize the currents through the digital potentiometer. the value that is written to this register will appear on the resistor network terminals when the serial command has completed. when the wl1 bit is enabled, writes to the tcon register bits r1hw, r1a, r1w, and r1b are inhibited. when the wl0 bit is enabled, writes to the tcon register bits r0hw, r0a, r0w, and r0b are inhibited. on a por/bor this register is loaded with 1ffh (9-bits), for all terminals connected. the host controller needs to detect the por/bor event and then update the volatile tcon register value. additionally, there is a bit which enables the operation of general call commands. register 4-2: tcon bits (address = 0x04) (1) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 gcen r1hw r1a r1w r1b r0hw r0a r0w r0b bit 8 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 8 gcen: general call enable bit this bit specifies if i 2 c general call commands are accepted 1 = enable device to ?accept? the general call address (0000h) 0 = the general call address is disabled bit 7 r1hw: resistor 1 hardware configuration control bit this bit forces resistor 1 into the ?shut down? configuration of the hardware pin 1 = resistor 1 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 1 is forced to the har dware pin ?shutdown? configuration bit 6 r1a: resistor 1 terminal a (p1a pin) connect control bit this bit connects/disconnects the resistor 1 terminal a to the resistor 1 network 1 = p1a pin is connected to the resistor 1 network 0 = p1a pin is disconnected from the resistor 1 network bit 5 r1w: resistor 1 wiper (p1w pin) connect control bit this bit connects/disconnects the resist or 1 wiper to the resistor 1 network 1 = p1w pin is connected to the resistor 1 network 0 = p1w pin is disconnected from the resistor 1 network bit 4 r1b: resistor 1 terminal b (p1b pin) connect control bit this bit connects/disconnects the resistor 1 terminal b to the resistor 1 network 1 = p1b pin is connected to the resistor 1 network 0 = p1b pin is disconnected from the resistor 1 network bit 3 r0hw: resistor 0 hardware configuration control bit this bit forces resistor 0 into the ?shut down? configuration of the hardware pin 1 = resistor 0 is not forced to the hardware pin ?shutdown? configuration 0 = resistor 0 is forced to the har dware pin ?shutdown? configuration bit 2 r0a: resistor 0 terminal a (p0a pin) connect control bit this bit connects/disconnects the resistor 0 terminal a to the resistor 0 network 1 = p0a pin is connected to the resistor 0 network 0 = p0a pin is disconnected from the resistor 0 network note 1: these bits do not affect the wiper register values.
? 2008 microchip technology inc. ds22091a-page 41 mcp454x/456x/464x/466x bit 1 r0w: resistor 0 wiper (p0w pin) connect control bit this bit connects/disconnects the resist or 0 wiper to the resistor 0 network 1 = p0w pin is connected to the resistor 0 network 0 = p0w pin is disconnected fr om the resistor 0 network bit 0 r0b: resistor 0 terminal b (p0b pin) connect control bit this bit connects/disconnects the resistor 0 terminal b to the resistor 0 network 1 = p0b pin is connected to the resistor 0 network 0 = p0b pin is disconnected from the resistor 0 network register 4-2: tcon bits (address = 0x04) (1) (continued) note 1: these bits do not affect the wiper register values.
mcp454x/456x/464x/466x ds22091a-page 42 ? 2008 microchip technology inc. 5.0 resistor network the resistor network has either 7-bit or 8-bit resolu- tion. each resistor netw ork allows zero scale to full-scale connections. figure 5-1 shows a block dia- gram for the resistive network of a device. the resistor network is made up of several parts. these include: ? resistor ladder ?wiper ? shutdown (terminal connections) devices have either one or two resistor networks, these are referred to as pot 0 and pot 1. figure 5-1: resistor block diagram. 5.1 resistor ladder module the resistor ladder is a series of equal value resistors (r s ) with a connection point (tap) between the two resistors. the total number of resistors in the series (ladder) determines the r ab resistance (see figure 5-1 ). the end points of the resistor ladder are connected to analog switches which are connected to the device terminal a and terminal b pins. the r ab (and r s ) resistance has small va riations over voltage and temperature. for an 8-bit device, there are 256 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal a and terminal b). for a 7-bit device, there are 128 resistors in a string between terminal a and terminal b. the wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal a and terminal b). equation 5-1 shows the calculation for the step resistance. equation 5-1: r s calculation r s a r s r s r s b 257 256 255 1 0 r w (1) w (01h) analog mux r w (1) (00h) r w (1) (feh) r w (1) (ffh) r w (1) (100h) note 1: the wiper resistance is dependent on several factors including, wiper code, device v dd , terminal voltages (on a, b, and w), and temperature. also for the same conditions, each tap selection resistance has a small variation. this r w variation has greater effects on some specifications (such as inl) for the smaller resistance devices (5.0 k ) compared to larger resistance devices (100.0 k ). r ab 8-bit n = 128 127 126 1 0 (01h) (00h) (7eh) (7fh) (80h) 7-bit n = r s r ab 256 () ------------- = r s r ab 128 () ------------- - = 8-bit device 7-bit device
? 2008 microchip technology inc. ds22091a-page 43 mcp454x/456x/464x/466x 5.2 wiper each tap point (between the r s resistors) is a connection point for an analog switch. the opposite side of the analog switch is connected to a common signal which is connected to the terminal w (wiper) pin. a value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the wiper can connect directly to terminal b or to terminal a. a zero-scale connections, connects the terminal w (wiper) to terminal b (wiper setting of 000h). a full-scale connections, connects the terminal w (wiper) to terminal a (wip er setting of 100h or 80h). in these configurations the only resistance between the terminal w and the other terminal (a or b) is that of the analog switches. a wiper setting value greater than full-scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a full-scale setting (terminal w (wiper) connected to terminal a). ta b l e 5 - 1 illustrates the full wiper setting map. equation 5-2 illustrates the calculation used to deter- mine the resistance between the wiper and terminal b. equation 5-2: r wb calculation table 5-1: volatile wiper value vs. wiper position map 5.3 wiperlock? technology the mcp4xxx device?s wiperlock technology allows application-specific calibration settings to be secured in the eeprom without requiring the use of an additional write-protect pin. there are two wiperlock technology configuration bits (wl0 and wl1). these bits prevent the non-volatile and volatile addresses and bits for the specified resistor netw ork from being written. the wiperlock technology prevents the serial commands from doing the following: ? changing a volatile wiper value ? writing to a non-volatile wiper memory location ? changing the volatile tcon register value for either resistor network 0 or resistor network 1 (potx), the wlx bit controls the following: ? non-volatile wiper register ? volatile wiper register ? volatile tcon register bits rxhw, rxa, rxw, and rxb high voltage commands are required to enable and disable wiperlock. please refer to the modify write protect or wiperlock technology (high voltage) command for operation. 5.3.1 por/bor operation when wiperlock technology enabled the wiperlock technology state is not affected by a por/bor event. a por/bor event will load the volatile wiper register value with the non-volatile wiper register value, refer to section 4.1 . table 5-1: wiper setting properties 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)), increment and decrement commands ignored 080h 100h full-scale (w = a), increment commands ignored 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) decrement command ignored r wb r ab n 256 () ------------- -r w + = n = 0 to 256 (decimal) r wb r ab n 128 () ------------- -r w + = n = 0 to 128 (decimal) 8-bit device 7-bit device
mcp454x/456x/464x/466x ds22091a-page 44 ? 2008 microchip technology inc. 5.4 shutdown shutdown is used to minimize the device?s current consumption. the mcp4xxx ac hieves this through the terminal control register (tcon) . 5.4.1 terminal control register (tcon) the terminal control (tcon) register is a volatile register used to configur e the connection of each resistor network terminal pin (a, b, and w) to the resistor network. this bits are described in register 4-2 . when the rxhw bit is a ? 0 ?, the selected resistor net- work is forced into the following state: ? the pxa terminal is disconnected ? the pxw terminal is simultaneously connected to the pxb terminal (see figure 5-2 ) ? the serial interface is not disabled, and all serial interface activity is executed ? any eeprom write cycles are completed alternate low power configurations may be achieved with the rxa, rxw, and rxb bits. figure 5-2: resistor network shutdown configuration. 5.4.2 interaction of rxhw bit and rxa, rxw, and rxb bits (tcon register) using the tcon bits allows each resistor network (pot 0 and pot 1) to be individually ?shutdown?. the state of the rxhw bit does not corrupt the other bit values in the tcon register nor the value of the volatile wiper registers. when the shutdown mode is exited (rxhw changes state from ? 0 ? to ? 1 ?): ? the device returns to the wiper setting specified by the volatile wiper value ? the rxa, rxb, and rxw bits return to controlling the terminal connection state of that resistor net- work note 1: the rxhw bits are identical to the rxhw bits of the mcp41xx/42xx devices. the mcp42xx devices also have a shdn pin which forces the resistor network into the same state as that resistor networks rxhw bit. 2: when rxhw = ?0?, the state of the tcon register rxa, rxw, and rxb bits is over- ridden (ignored). when the state of the rxhw bit returns to ?1?, the tcon register rxa, rxw, and rxb bits return to controlling the terminal connection state. in other words, the rxhw bit does not corrupt the state of the rxa, rxw, and rxb bits. a b w resistor network
? 2008 microchip technology inc. ds22091a-page 45 mcp454x/456x/464x/466x 6.0 serial interface (i 2 c) the mcp45xx/46xx devices support the i 2 c serial protocol. the mcp45xx/46xx i 2 c?s module operates in slave mode (does not generate the serial clock). figure 6-1 shows a typical i 2 c interface connection. all i 2 c interface signals are high-voltage tolerant. the mcp45xx/46xx devices use the two-wire i 2 c serial interface. this inte rface can operate in standard, fast or high-speed mode. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions. the mcp45xx/46xx device works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. communi- cation is initiated by the ma ster (microcontroller) which sends the start bit, followed by the slave address byte. the first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the r/w bit. refer to the phillips i 2 c document for more details of the i 2 c specifications. figure 6-1: typical i 2 c interface block diagram. 6.1 signal descriptions the i 2 c interface uses up to five pins (signals). these are: ? sda (serial data) ? scl (serial clock) ? a0 (address 0 bit) ? a1 (address 1 bit) ? a2 (address 2 bit) 6.1.1 serial data (sda) the serial data (sda) signal is the data signal of the device. the value on this pin is latched on the rising edge of the scl signal when the signal is an input. with the exception of the start and stop conditions, the high or low state of the sda pin can only change when the clock signal on the scl pin is low. during the high period of the clock the sda pin?s value (high or low) must be stable. changes in the sda pin?s value while the scl pin is high will be interpreted as a start or a stop condition. 6.1.2 serial clock (scl) the serial clock (scl) signal is the clock signal of the device. the rising edge of the scl signal latches the value on the sda pin. the mcp45xx/46xx supports three i 2 c interface clock modes: ? standard mode: clock rates up to 100 khz ? fast mode: clock rates up to 400 khz ? high-speed mode (hs mode): clock rates up to 3.4 mhz the mcp4xxx will not strech the clock signal (scl) since memory read acceses occur fast enough. depending on the clock rate mode, the interface will display different characteristics. 6.1.3 the address bits (a2:a1:a0) there are up to three hardware pins used to specify the device address. the number of adress pins is determined by the part number. address 0 is multiplexed with the high voltage command (hvc) function. so the state of a0 is latched on the mcp4xxx?s por/bor event. the state of the a2 and a1 pins should be static, that is they should be tied high or tied low. 6.1.3.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multi- plexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. scl (2) scl mcp4xxx sda (2) sda hvc/a0 (2) i/o (1) host controller typical i 2 c interface connections note 1: if high voltage commands are desired, some type of external circuitry needs to be implemented. 2: these pins have internal pull-ups. if faster rise times are required, then external pull-ups should be added. 3: this pin could be tied high, low, or connected to an i/o pin of the host controller. a1 (2, 3) a2 (2, 3)
mcp454x/456x/464x/466x ds22091a-page 46 ? 2008 microchip technology inc. 6.2 i 2 c operation the mcp45xx/46xx?s i 2 c module is compatible with the philips i 2 c specification. the following lists some of the modules features: ? 7-bit slave addressing ? supports three clock rate modes: - standard mode, clock rates up to 100 khz - fast mode, clock rates up to 400 khz - high-speed mode (hs mode), clock rates up to 3.4 mhz ? support multi-master applications ? general call addressing ? internal weak pull-ups on interface signals the i 2 c 10-bit addressing mode is not supported. the philips i 2 c specification only defines the field types, field lengths, timings, etc. of a frame. the frame content defines the behavior of the device. the frame content for the mcp4xxx is defined in section 7.0 . 6.2.1 i 2 c bit states and sequence figure 6-8 shows the i 2 c transfer sequence. the serial clock is generated by the master. the following defini- tions are used for the bit states: ? start bit (s) ? data bit ? acknowledge (ack) bit (driven low) / no acknowledge (nack) bit (not driven low) ? repeated start bit (sr) ? stop bit (p) 6.2.1.1 start bit the start bit (see figure 6-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is ?high?. figure 6-2: start bit. 6.2.1.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 6-5 ). figure 6-3: data bit. 6.2.1.3 acknowledge (ack ) bit the ack bit (see figure 6-4 ) is typically a response from the receiving device to the transmitting device. depending on the context of the transfer sequence, the ack bit may indicate different things. typically the slave device will supply an ack response after the start bit and 8 ?data? bits have been received. an ack bit has the sda signal low. figure 6-4: acknowledge waveform. not ack (nack ) response the nack bit has the sda signal high. table 6-1 shows some of the conditi ons where the slave device will issue a not ack (nack ). if an error condition occurs (such as an n ack instead of ack ) then an start bit must be issued to reset the command state machine. table 6-1: mcp45xx/mcp46xx ack / nack responses sda scl s 1st bit 2nd bit sda scl data bit 1st bit 2nd bit event ack bit response comment general call ack only if gcen bit is set slave address valid ack slave address not valid nack device mem- ory address and specified command (ad3:ad0 and c1:c0) are an invalid combi- nation nack after device has received address and command communica- tion during eeprom write cycle ack after device has received address and command, and valid conditions for eeprom write bus collision n.a. i 2 c module resets, or a ?don?t care? if the collision occurs on the masters ?start bit?. ack 8 d0 9 sda scl
? 2008 microchip technology inc. ds22091a-page 47 mcp454x/456x/464x/466x 6.2.1.4 repeated start bit the repeated start bit (see figure 6-5 ) indicates the current master device wishe s to continue communicat- ing with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + ack bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is ?high?. figure 6-5: repeat start condition waveform. 6.2.1.5 stop bit the stop bit (see figure 6-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is ?high?. a stop bit resets the i 2 c interface of all mcp4xxx devices. figure 6-6: stop condition receive or transmit mode. 6.2.2 clock stretching ?clock stretching? is some thing that the receiving device can do, to allow additional time to ?respond? to the ?data? that has been received. the mcp4xxx will not strech the clock signal (scl) since memory read acceses occur fast enough. 6.2.3 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is abort ed. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. figure 6-7: typical 8-bit i 2 c waveform format. figure 6-8: i 2 c data states and bit sequence. note 1: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". sda scl sr = repeated start 1st bit scl sda ack p 1st bit sda scl s 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit p ack / nack scl sda start condition stop condition data allowed to change data or ack valid
mcp454x/456x/464x/466x ds22091a-page 48 ? 2008 microchip technology inc. 6.2.4 addressing the address byte is the first byte received following the start condition from the master device. the address contains four (or more) fixed bits and (up to) three user defined hardware address bits (pins a2, a1, and a0). these 7-bits address the desired i 2 c device. the a7:a4 address bits are fixed to ? 0101 ? and the device appends the value of following three address pins (a2, a1, a0). address pins that are not present on the device are pulled up (a bit value of ? 1 ?). since there are up to three adress bits controlled by hardware pins, there may be up to eight mcp4xxx devices on the same i 2 c bus. figure 6-9 shows the slave address byte format, which contains the seven address bits. there is also a read/ write bit. ta b l e 6 - 2 shows the fixed address for device. hardware address pins the hardware address bits (a2, a1, and a0) correspond to the logic level on the associated address pins. this allows up to eight devices on the bus. these pins have a weak pull-up enabled when the v dd < v bor . the weak pull-up utilizes the ?smart? pull-up technology and exhibits the same characteristics as the high-voltage tolerant i/o structure. the state of the a0 addre ss pin is latch on por/bor. this is required since high voltage commands force this pin (hvc/a0) to the v ihh level. figure 6-9: slave address bits in the i 2 c control byte. table 6-2: device slave addresses 6.2.5 slope control the mcp45xx/46xx implements slope control on the sda output. as the device transitions from hs mode to fs mode, the slope control parmameter will change from the hs specification to the fs specification. for fast (fs) and high-speed (hs) modes, the device has a spike suppression and a schmidt trigger at sda and scl inputs. device address comment mcp45x1 ? 0101 11 ?b + a0 supports up to 2 devices. note 1 mcp45x2 ? 0101 1 ?b + a1:a0 supports up to 4 devices. note 1 mcp46x1 ? 0101 ?b + a2:a1:a0 supports up to 8 devices. note 1 mcp46x2 ? 0101 1 ?b + a1:a0 supports up to 4 devices. note 1 note 1: a0 is used for high-voltage commands and the value is latched at por. sa6a5a4a3 a2 a1 a0 r/w ack start bit slave address r/w bit ack bit (controlled by slave device) r/w = 0 = write r/w = 1 = read ack = 0 = slave device acknowledges byte ack = 1 = slave device does not acknowledge byte ?0? ?1? ?0? ?1? see table 6-2
? 2008 microchip technology inc. ds22091a-page 49 mcp454x/456x/464x/466x 6.2.6 hs mode the i 2 c specification requires that a high-speed mode device must be ?activated? to operate in high-speed (3.4 mbit/s) mode. this is done by the master sending a special address byte following the start bit. this byte is referred to as the high-speed master mode code (hsmmc). the mcp45xx/46xx device does not acknowledge this byte. however, upon receiving this command, the device switches to hs mode. the device can now com- municate at up to 3.4 mbit/s on sda and scl lines. the device will switch out of the hs mode on the next stop condition. the master code is sent as follows: 1. start condition (s) 2. high-speed master mode code ( 0000 1xxx ), the xxx bits are unique to the high-speed (hs) mode master. 3. no acknowledge (a ck ) after switching to the high-speed mode, the next transferred byte is the i 2 c control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. the master device can then either issue a repeated start bit to address a different device (at high-speed) or a stop bit to return to fast/standard bus speed. after the stop bit, any other master device (in a multi-master system) can arbitrate for the i 2 c bus. see figure 6-10 for illustration of hs mode command sequence. for more information on the hs mode, or other i 2 c modes, please refer to the phillips i 2 c specification. 6.2.6.1 slope control the slope control on the sda output is different between the fast/standard speed and the high-speed clock modes of the interface. 6.2.6.2 pulse gobbler the pulse gobbler on the scl pin is automatically adjusted to suppress spikes < 10 ns during hs mode. figure 6-10: hs mode sequence. s a ?0 0 0 0 1 x x x?b sr a ?slave address? a /a ?data? p s = start bit sr = repeated start bit a = acknowledge (ack) bit a = not acknowledge (ack ) bit r/w = read/write bit r/w p = stop bit (stop condition terminates hs mode) f/s-mode hs-mode hs-mode continues f/s-mode sr a ?slave address? r/w hs select byte control byte command/data byte(s) control byte
mcp454x/456x/464x/466x ds22091a-page 50 ? 2008 microchip technology inc. 6.2.7 general call the general call is a method that the ?master? device can communicate with all other ?slave? devices. in a multi-master application, t he other master devices are operating in slave mode. the general call address has two documented formats. these are shown in figure 6-11 . we have added a mcp45xx/46xx format in this figure as well. this will allow customers to have multiple i 2 c digital potentiometers on the bus and have them operate in a synchronous fashion (analogous to the dac sync pin functionality). if these mcp45xx/46xx 7-bit com- mands conflict with other i 2 c devices on the bus, then the customer will need two i 2 c busses and ensure that the devices are on the correct bus for their desired application functionality. dual pot devices can not update both pot0 and pot1 from a single command. to address this, there are general call commands for the wiper 0, wiper 1, and the tcon registers. table 6-3 shows the general call commands. three commands are specified by the i 2 c specification and are not applicable to the mcp45xx/46xx (so com- mand is nack ?d) the mcp45xx/46xx general call commands are ack ?d. any other command is not ack ?d. table 6-3: general call commands note: only one general call command per issue of the general call control byte. any addi- tional general call commands are ignored and nack ?d. 7-bit command (1, 2, 3) comment ?1000 00d?b write next byte (third byte) to volatile wiper 0 register ?1001 00d?b write next byte (third byte) to volatile wiper 1 register ?1100 00d?b write next byte (third byte) to tcon register ?1000 010?b or ?1000 011?b increment wiper 0 register ?1001 010?b or ?1001 011?b increment wiper 1 register ?1000 100?b or ?1000 101?b decrement wiper 0 register ?1001 100?b or ?1001 101?b decrement wiper 1 register note 1: any other code is not ack ?d (nack ). these codes may be used by other devices on the i 2 c bus. 2: the 7-bit command always appends a ?0? to form 8-bits. . 3: ?d? is the d8 bit for the 9-bit write value.
? 2008 microchip technology inc. ds22091a-page 51 mcp454x/456x/464x/466x figure 6-11: general call formats. 0 000 s 0000 x xxxx a xx0ap general call address second byte ?7-bit command? reserved 7-bit commands (by i 2 c specification - philips # 9398 393 40011, ver. 2.1 january 2000) ?0000 011? b - reset and write programmable part of slave address by hardware. ?0000 010? b - write programmable part of slave address by hardware. ?0000 000? b - not allowed mcp45xx/mcp46xx 7-bit commands ?1000 01x? b - increment wiper 0 register. ?1001 01x? b - increment wiper 1 register. the following is a microchip extension to this general call format 0 000 s 0000 x xxxx axd0a general call address second byte ?7-bit command? mcp45xx/mcp46xx 7-bit commands ?1000 00d? b - write next byte (third byte) to volatile wiper 0 register. ?1001 00d? b - write next byte (third byte) to volatile wiper 1 register. d dddd dddap third byte the following is a ?hardware general call? format 0 000 s 0000 x xxxx axx1a general call address second byte ?7-bit command? x xxxx xxxap n occurrences of (data + ack) this indicates a ?hardware general call? mcp45xx/mcp46xx will ignore this byte and all following bytes (and not ack), until ? 1000 10x? b - decrement wiper 0 register. ?1001 10x? b - decrement wiper 1 register. ?1100 00d? b - write next byte (third byte) to tcon register. a stop bit (p) is encountered. ?0? for general call command
mcp454x/456x/464x/466x ds22091a-page 52 ? 2008 microchip technology inc. 6.2.8 i 2 c i/o considerations the mcp4xxx?s i 2 c i/o are high voltage tolerant and incorporate pull-up/down to v dd functionality. this pre- vents the i/o from floating in situations where no exter- nal resistor was included in the application. this would be common in applications where the mcp4xxx?s i 2 c interface is used during factory calibration but not used by the application. the sda and scl float (are not driving) when the device?s v dd is below the minimum operating voltage. note 1: the sda?s pull-up is enabled whenever the device is not driving the pin (low). 2: the scl pin uses a pull-up, since this pin is never an output. note 1: the sda and scl signals have a weak pull-up to the internal system bus. so voltages on these signals while the device v dd is powered down, will power the mcp4xxx. powering the device through the sda or scl pins is not specified operation.
? 2008 microchip technology inc. ds22091a-page 53 mcp454x/456x/464x/466x 7.0 device commands the mcp4xxx?s i 2 c command formats are specified in this section. the i 2 c protocol does not specify how commands are formatted. the mcp4xxx supports four basic commands. depending on the location accessed determines the commands that are supported. for the volatile wiper regi sters, these commands are: ? write data ? read data ? increment data ? decrement data for the non-volatile wi per eeprom, general purpose data eeprom, and the tcon register these com- mands are: ? write data ? read data these commands have formats for both a single command or continuous commands. these commands are shown in table 7-1 . each command has two operational states. the operational state determines if the device commands control the special features (write protect and wiper- lock technology). these operational states are referred to as: ? normal serial commands ? high-voltage serial commands table 7-1: i 2 c commands normal serial commands are those where the hvc pin is driven to v ih or v il . with high-voltage serial com- mands, the hvc pin is driven to v ihh . in each mode, there are four possible commands. additionally, there are two commands used to enable or disable the special features (write protect and wiper lock technology) of the device. the commands are special cases of the increment and decrement high-voltage serial command. table 7-2 shows the supported commands for each memory location. table 7-3 shows an overview of all the device com- mands and their interaction with other device features. 7.1 command byte the mcp4xxx?s command byte has three fields: the address, the command oper ation, and 2 data bits, see figure 7-1 . currently only one of the data bits is defined (d8). the device memory is accessed when the master sends a proper command byte to select the desired operation. the memory location getting accessed is contained in the command byte?s ad3:ad0 bits. the action desired is contained in the command byte?s c1:c0 bits, see ta b l e 7 - 1 . c1:c0 determines if the desired memory location will be read, written, incremented (wiper setting +1) or decremented (wiper setting -1). the increment and decrement commands are only valid on the volat ile wiper registers, and in high voltage commands to enable/disable wiperlock technology and software write protect. if the address bits and command bits are not a valid combination, then the mcp4xxx will generate a nack pulse to indicate the invalid combination. the i 2 c master device must then force a start condition to reset the mcp4xxx?s 2 c module. d9 and d8 are the most significant bits for the digital potentiometer?s wiper setting. the 8-bit devices utilize d8 as their msb while the 7-bit devices utilize d7 (from the data byte) as it?s msb. figure 7-1: command byte format. command # of bit clocks (1) operates on volatile/ non-volatile memory operation mode write data single 29 both continuous 18n + 11 volatile only read data single 29 both random 48 both continuous 18n + 11 both (2) increment (3) single 20 volatile only continuous 9n + 11 volatile only decrement (3) single 20 volatile only continuous 9n + 11 volatile only note 1: ?n? indicates the number of times the command operation is to be repeated. 2: this command is useful to determine if a non-volatile memory write cycle has completed. 3: high voltage increment and decrement commands on select non-volatile memory locations enable/disable wiperlock technology and the software write protect feature. a c k a d 3 a d 2 a d 1 a d 0 c 1 c 0 d 9 d 8 a c k mcp4xxx command byte 00 = write data 01 = increment msbits (data) 10 = decrement 11 = read data command operation bits memory address
mcp454x/456x/464x/466x ds22091a-page 54 ? 2008 microchip technology inc. table 7-2: memory map and the supported commands address command operation data (10-bits) (1) comment value function 00h volatile wiper 0 write data nn nnnn nnnn read data (3) nn nnnn nnnn increment wiper ? decrement wiper ? 01h volatile wiper 1 write data nn nnnn nnnn read data (3) nn nnnn nnnn increment wiper ? decrement wiper ? 02h non volatile wiper 0 write data nn nnnn nnnn read data (3) nn nnnn nnnn high voltage increment ? wiper lock 0 disable high voltage decrement ? wiper lock 0 enable 03h non volatile wiper 1 write data nn nnnn nnnn read data (3) nn nnnn nnnn high voltage increment ? wiper lock 1 disable high voltage decrement ? wiper lock 1 enable 04h (2) volatile tcon register write data nn nnnn nnnn read data (3) nn nnnn nnnn 05h (2) status register read data (3) nn nnnn nnnn 06h (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 07h (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 08h (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 09h (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 0ah (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 0bh (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 0ch (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 0dh (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 0eh (2) data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn 0fh data eeprom write data nn nnnn nnnn read data (3) nn nnnn nnnn high voltage increment ? write protect disable high voltage decrement ? write protect enable note 1: the data memory is only 9-bits wide, so the msb is ignored by the device. 2: increment or decrement commands are invalid for these addresses. 3: i 2 c read operation will read 2 bytes, of whic h the 10-bits of data are contained within.
? 2008 microchip technology inc. ds22091a-page 55 mcp454x/456x/464x/466x 7.2 data byte only the read command and the write command have data byte(s). the write command concatenates the 8-bits of the data byte with the one data bit (d8) contained in the command byte to form 9-bits of data (d8:d0). the command byte format supports up to 9-bits of data so that the 8-bit resistor netw ork can be set to full-scale (100h or greater). this allows wiper connections to terminal a and to terminal b. the d9 bit is currently unused. 7.3 error condition if the four address bits received (ad3:ad0) and the two command bits received (c1:c0) are a valid combina- tion, the mcp4xxx will ack the i 2 c bus. if the address bits and command bits are an invalid combination, then the mcp4xxx will nack the i 2 c bus. once an error condition has occurred, any following commands are ignored until the i 2 c bus is reset with a start condition. 7.3.1 aborting a transmission a restart or stop condition in the expected data bit position will abort the current command sequence and data will not be wr itten to the mcp4xxx. table 7-3: commands command name writes value in eeprom operates on volatile/ non-volatile memory high voltage (v ihh ) on hvc pin? impact on wiperlock or write protect works when wiper is ?locked?? write data normal and high voltage yes (1) both ? unlocked (1) no read data ? both ? unlocked (1) no increment wiper ? volatile only ? unlocked (1) no decrement wiper ? volatile only ? unlocked (1) no high voltage write data normal and high voltage yes both yes unchanged no high voltage read data ? both yes unchanged yes high voltage increment wiper ? volatile only yes unchanged no high voltage decrement wiper ? volatile only yes unchanged no modify write protect or wiperlock technology (high voltage) - enable ? (2) non-volatile only (2) yes locked/ protected (2) yes modify write protect or wiperlock technology (high voltage) - disable ? (3) non-volatile only (3) yes unlocked/ unprotected (3) yes note 1: this command will only complete, if wiper is ?unlocked? (wiperlock technology is disabled). 2: if the command is executed using address 02h or 03h, that corresponding wiper is locked or if with address 0fh, then write protect is enabled. 3: if the command is executed using with address 02h or 03h, that corresponding wiper is unlocked or if with address 0fh, then write protect is disabled.
mcp454x/456x/464x/466x ds22091a-page 56 ? 2008 microchip technology inc. 7.4 write data normal and high voltage the write command can be issued to both the volatile and non-volatile memory locations. the format of the command, see figure 7-2 , includes the i 2 c control byte, an ack bit, the mcp4xxx command byte, an ack bit, the mcp4xxx data byte, an ack bit, and a stop (or restart) condi tion. the mcp4xxx generates the ack / nack bits. a write command to a volatile memory location changes that location after a properly formatted write command and the ack / nack clock have been received. a write command to a non-volatile memory location will only start a write cycle after a properly formatted write command have been received and the stop condition has occurred. 7.4.1 single write to volatile memory for volatile memory locations, data is written to the mcp4xxx after every byte tr ansfer (during the ack). if a stop or restart conditi on is generated during a data transfer (before the ack ), the data will not be written to the mcp4xxx. after the ack bit, the master can initiate the next sequenc e with a stop or restart condition. refer to figure 7-2 for the byte write sequence. 7.4.2 single write to non-volatile memory the sequence to write to a single non-volatile memory location is the same as a single write to volatile memory with the exception that the eeprom write cycle (t wc ) is started after a properly formatted command, including the stop bit, is received. after the stop condition occurs the serial interface may immediately be re-enabled by initiating a start condition. during an eeprom write cycl e, access to volatile memory (addresses 00h, 01h, 04h, and 05h) is allowed when using the appropriate command sequence. commands that address non-volatile memory are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile wiper registers, the tcon register, and to read the status register. the eewa bit in the status register indicates the st atus of an eeprom write cycle. once a write command to a non-volatile memory location has been received, no other commands should be received before the stop condition occurs. figure 7-2 show the waveform for a single write. 7.4.3 continuous writes to volatile memory a continuous write mode of operation is possible when writing to the volatile me mory registers (address 00h, 01h, and 04h). this continuous write mode allows writes without a stop or re start condition or repeated transmissions of the i 2 c control byte. figure 7-3 shows the sequence for thr ee continuous writes. the writes do not need to be to the same volatile memory address. the sequence ends with the master sending a stop or restart condition. 7.4.4 continuous writes to non-volatile memory if a continuous write is attempted on non-volatile memory, the missing stop condition will cause the command to be an error condition (nack ). a start bit is required to reset the command state machine. 7.4.5 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or seque nce of commands, are in the high voltage operational state. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. note: writes to certain memory locations will be dependant on the state of the wiperlock technology bits and the write protect bit.
? 2008 microchip technology inc. ds22091a-page 57 mcp454x/456x/464x/466x figure 7-2: i 2 c write sequence. figure 7-3: i 2 c continuous volatile wiper write. control byte write command write data bits 1 010 sa2a1a00 0 ad ad ad ad a0xd8ad3 d7 d6 d5 d4 d2 d1 d0 a p 0 1 2 3 fixed address variable address device memory address command write ?data? bits write bit stop bit control byte write command write data bits 1 010 sa2a1a00 0 a0xd8ad3 d7 d6 d5 d4 d2 d1 d0 a fixed address variable address device memory address command write ?data? bits write command write data bits 00xd8a d3 d7 d6 d5 d4 d2 d1 d0 a write command write data bits 00xd8a d3 d7 d6 d5 d4 d2 d1 d0 a p write bit ad ad ad ad 0 1 2 3 ad ad ad ad 0 1 2 3 ad ad ad ad 0 1 2 3 note: only functions when writing the volatile wiper registers (ad3:ad0 = 00h, 01h, and 04h) or the tcon register
mcp454x/456x/464x/466x ds22091a-page 58 ? 2008 microchip technology inc. 7.5 read data normal and high voltage the read command can be issued to both the volatile and non-volatile memory locations. the format of the command, see figure 7-4 , includes the start condition, i 2 c control byte (with r/ w bit set to ?0?), ack bit, mcp4xxx command byte, ack bit, followed by a repeated start bit, i 2 c control byte (with r/w bit set to ?1?), and the mcp4xxx tran smitting the requested data high byte, and ack bit, the data low byte, the master generating the nack (no ack ), and stop condition. the i 2 c control byte requires the r/w bit equal to a logic one (r/w = 1) to generate a read sequence. the memory location read will be the last address contained in a valid writ e mcp4xxx command byte or address 00h if no write operations have occurred since the device was reset (power-on reset or brown-out reset). during a write cycle (write or high voltage write to a non-volatile memory location) the read command can only read the volatile memory locations. by reading the status register (04h), the host controller can determine when the write cycl e has completed (via the state of the eewa bit). read operations initially include the same address byte sequence as the write sequence (shown in figure 6-9 ). this sequence is followed by another control byte (including the start condition and ack ) with the r/w bit equal to a logic one (r/w = 1) to indicate a read. the mcp4xxx will then transmit the data contained in the addressed register. this is followed by the master generating an ack in prepara- tion for more data, or a nack followed by a stop. the sequence is ended with the master generating a stop or restart condition. the internal address pointer is maintained. if this address pointer is for a non-volatile memory address and the read control byte addresses the device during a non-volatile write cycle (t wc ) the device will respond with a nack. 7.5.1 single read figure 7-4 show the waveforms for a single read. for single reads the master sends a stop or restart condition after the data byte is sent from the slave. 7.5.1.1 random read figure 7-5 shows the sequence for a random reads. refer to figure 7-5 for the random byte read sequence. 7.5.2 continuous reads continuous reads allows the devices memory to be read quickly. continuous reads are possible to all memory locations. if a non- volatile memo ry write cycle is occurring, then read commands may only access the volatile memory locations. figure 7-6 shows the sequence for three continuous reads. for continuous reads , instead of transmitting a stop or restart condition after the data transfer, the master reads the next data byte. the sequence ends with the master nacking and then sending a stop or restart. 7.5.3 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or seque nce of commands, are in the high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp4xxxs internal v dd signal. 7.5.4 ignoring an i 2 c transmission and ?falling off? the bus the mcp4xxx expects to receive entire, valid i 2 c commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the sda signal. all signals will be ignored until the next valid start condition and control byte are received.
? 2008 microchip technology inc. ds22091a-page 59 mcp454x/456x/464x/466x figure 7-4: i 2 c read (last memory address accessed). figure 7-5: i 2 c random read. stop bit control byte 1 010 sa2a1a01a fixed address variable address read bits p 0 000 0 0 0d8a 1 read bit d3 d7 d6 d5 d4 d2 d1 d0 a 2 read data bits note 1: master device is responsible for ack / nack signal. if a nack signal occurs, the mcp45xx/ 46xx will abort this transfer and release the bus. 2: the master device will not ack , and the mcp45xx/46xx will release the bus so the master device can generate a stop or repeated start condition. 3: the mcp45xx/46xx retains the last ?device memory address? that it has received. this is the mcp45xx/46xx does not ?corrupt? the ?device memory address? after repeated start or stop conditions. 4: the device memory address pointer def aults to 00h on por and bor conditions. stop bit control byte read command 1 010 sa2a1a00 1 ad ad ad ad a1xxasr 0 1 2 3 fixed address variable address device memory address command control byte read bits p 0 000 0 0 0d8a 1 write bit d3 d7 d6 d5 d4 d2 d1 d0 a 2 1 010 a2a1a01 a read bit repeated start bit read data bits note 1: master device is responsible for ack / nack signal. if a nack signal occurs, the mcp45xx/ 46xx will abort this transfer and release the bus. 2: the master device will not ack , and the mcp45xx/46xx will release the bus so the master device can generate a stop or repeated start condition. 3: the mcp45xx/46xx retains the last ?device memo ry address? that it has received. this is the mcp45xx/46xx does not ?corru pt? the ?device memory address? after repeated start or stop conditions.
mcp454x/456x/464x/466x ds22091a-page 60 ? 2008 microchip technology inc. figure 7-6: i 2 c continuos reads. stop bit control byte 1 010 sa2a1a01a fixed address variable address read bits 0 000 0 0 0d8a 1 read bit d3 d7 d6 d5 d4 d2 d1 d0 a 1 read data bits 0 000 0 0 0d8a 1 d3 d7 d6 d5 d4 d2 d1 d0 a 1 p 0 000 0 0 0d8a 1 d3 d7 d6 d5 d4 d2 d1 d0 a 2 read data bits read data bits note 1: master device is responsible for ack / nack signal. if a nack signal occurs, the mcp45xx/ 46xx will abort this transfer and release the bus. 2: the master device will not ack , and the mcp45xx/46xx will release the bus so the master device can generate a stop or repeated start condition.
? 2008 microchip technology inc. ds22091a-page 61 mcp454x/456x/464x/466x 7.6 increment wiper normal and high voltage the increment command provide a quick and easy method to modify the potenti ometer?s wiper by +1 with minimal overhead. the increment command will only function on the volatile wiper setting memory locations 00h and 01h. the increment command to non-volatile addresses will be ignored and will generate a nack . when executing an increment command, the volatile wiper setting will be altered from n to n+1 for each increment command received. the value will incre- ment up to 100h max on 8-bit devices and 80h on 7-bit devices. if multiple incr ement commands are received after the value has reached 100h (or 80h), the value will not be incremented further. ta b l e 7 - 4 shows the increment command versus the current volatile wiper value. the increment command will most commonly be performed on the volatile wiper locations until a desired condition is met. the value in the volatile wiper register would need to be read using a read operation in order to write the new setting to the corresponding non-volatile wiper memory using a write operation. the mcp4xxx is responsible for generating the ack bits. refer to figure 7-7 for the increment command sequence. the sequence is terminated by the stop condition. so when executing a continuous command string, the increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. the advantage of using an increment command instead of a read-modify-wr ite series of commands is speed and simplicity. the wiper will transition after each command ack when accessing the volatile wiper registers. table 7-4: increment operation vs. volatile wiper value 7.6.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multi- plexed with address 0 (a0) and is used to indicate that the command, or sequence of commands, are in the high voltage mode. signals > v ihh (~8.5v) on the hvc/a0 pin puts mcp45xx/46xx devices into high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. figure 7-7: i 2 c increment command sequence. note: table 7-2 shows the valid addresses for the increment wiper command. other addresses are invalid. note: the command sequence can go from an increment to any other valid command for the specified address. issuing an incre- ment or decrement to a non-volatile loca- tion will cause an error condition (nack will be generated). current wiper setting wiper (w) properties increment command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) no 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) yes note: there is a required delay after the hvc pin is driven to the v ihh level to the 1st edge of the scl pin. control byte incr command (n+1) incr command (n+2) 1 010 sa2a1a00 0 ad ad ad ad a1xxa0 ad ad ad ad 1x x a p (2) 0 1 2 3 4321 fixed address variable address device memory address command write bit note 1: increment command (incr) only functions when accessing the volatile wiper reg- isters (ad3:ad0 = 0h and 1h). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired command sequence (increment, read, or write).
mcp454x/456x/464x/466x ds22091a-page 62 ? 2008 microchip technology inc. 7.7 decrement wiper normal and high voltage the decrement command provide a quick and easy method to modify the potentiometer?s wiper by -1 with minimal overhead. the decrement command will only function on the volatile wiper setting memory locations 00h and 01h. decrement commands to non-volatile addresses will be ignored and will generate a nack . when executing a decrement command, the volatile wiper setting will be altered from n to n-1 for each decrement command received. the value will decrement down to 000h min. if multiple decrement commands are received after the value has reached 000h, the value will not be decremented further. table 7-5 shows the increment command versus the current volatile wiper value. the decrement command will most commonly be performed on the volatile wiper locations until a desired condition is met. the value in the volatile wiper register would need to be read using a read operation in order to write the new setting to the corresponding non-volatile wiper memory using a write operation. the mcp4xxx is responsible for generat ing the ack bits. refer to figure 7-8 for the decrement command sequence. the sequence is terminated by the stop condition. so when exec uting a continuous command string, the increment command can be followed by any other valid command. this means that writes do not need to be to the same volatile memory address. the advantage of using an decrement command instead of a read-modify-wr ite series of commands is speed and simplicity. the wiper will transition after each command ack when accessing the volatile wiper registers. table 7-5: decrement operation vs. volatile wiper value 7.7.1 the high voltage command (hvc) signal the high voltage command (hvc) signal is multiplexed with address 0 (a0) and is used to indicate that the command, or seque nce of commands, are in the high voltage mode. signals > v ihh (~8.5v) on the hvc/a0 pin puts mcp45xx/46xx devices into high voltage mode. high voltage commands allow the device?s wiperlock technology and write protect features to be enabled and disabled. the hvc pin has an internal resistor connection to the mcp45xx/46xxs internal v dd signal. figure 7-8: i 2 c decrement command sequence. note: table 7-2 shows the valid addresses for the decrement wiper command. other addresses are invalid. note: the command sequence can go from an increment to any other valid command for the specified address. issuing an increment or decrement to a non-volatile location will cause an error condition (nack will be generated). current wiper setting wiper (w) properties decrement command operates? 7-bit pot 8-bit pot 3ffh 081h 3ffh 101h reserved (full-scale (w = a)) no 080h 100h full-scale (w = a) yes 07fh 041h 0ffh 081 w = n 040h 080h w = n (mid-scale) yes 03fh 001h 07fh 001 w = n 000h 000h zero scale (w = b) no note: there is a required delay after the hvc pin is driven to the v ihh level to the 1st edge of the scl pin. control byte decr command (n-1) decr command (n-2) 1 010 sa2a1a00 1 ad ad ad ad a0xxa1 ad ad ad ad 0x xap (2) 0 1 2 3 4321 fixed address variable address device memory address command write bit note 1: decrement command (decr) only functions when accessing the volatile wiper registers (ad3:ad0 = 0h and 1h). 2: this command sequence does not need to terminate (using the stop bit) and can change to any other desired comman d sequence (incr, read, or write).
? 2008 microchip technology inc. ds22091a-page 63 mcp454x/456x/464x/466x 7.8 modify write protect or wiperlock technology (high voltage) enable and disable these commands are special cases of the high volt- age decrement wiper and the high voltage incre- ment wiper commands to the non-volatile memory locations 02h, 03h, and 0fh. this command is used to enable or disable either the software write protect, wiper 0 wiperlock technology, or wiper 1 wiperlock technology. table 7-6 shows the memory addresses, the high voltage command and the result of those commands on the non-volatile wp, wl0, 0r wl1 bits. 7.8.1 single modify (enable or disable) write protect or wiperlock technology (high voltage) figure 7-9 (disable) and figure 7-10 (enable) show the formats for a single modify write protect or wiper- lock technology command. a modify write protect or wiperlock technology command will only start an eeprom write cycle (t wc ) after a properly formatted command has been received and the stop condition occurs. during an eeprom write cycl e, only serial commands to volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. all other serial commands are ignored until the eeprom write cycle (t wc ) completes. this allows the host controller to operate on the volatile wiper registers and the tcon register, and to read the status register. the eewa bit in the status register indicate s the status of an eeprom write cycle. table 7-6: address map to modify write protect and wiperlock technology figure 7-9: i 2 c disable command sequence. figure 7-10: i 2 c enable command sequence. memory address command?s and result high voltage decrement wiper high voltage increment wiper 00h wiper 0 register is incremented wiper 0 register is incremented 01h wiper 1 register is incremented wiper 1 register is incremented 02h wl0 is enabled wl0 is disabled 03h wl1 is enabled wl1 is disabled 04h (1) tcon register not changed tcon register not changed 05h - 0eh (1) reserved reserved 0fh wp is enabled wp is disabled note 1: reserved addresses: increment or decrement commands are invalid for these addresses. control byte disable command 1 010 sa2a1a00 0 ad ad ad ad a1xxa p 1 2 3 fixed address variable address device memory address command (increment) write bit 0 control byte enable command 1 010 sa2a1a00 1 ad ad ad ad a0xxa p 0 1 2 3 fixed address variable address device memory address command (decrement) write bit
mcp454x/456x/464x/466x ds22091a-page 64 ? 2008 microchip technology inc. 8.0 applications examples non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. the most popular uses include precision calibration of set point thresholds, sensor trimming, lcd bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. the mcp454x/456x/464x/466x devices can be used to replace the common mechani- cal trim pot in applicatio ns where the operating and terminal voltages are within cmos process limitations (v dd = 2.7v to 5.5v). 8.1 techniques to force the hvc pin to v ihh the circuit in figure 8-1 shows a method using the tc1240a doubling charge pump. when the shdn pin is high, the tc1240a is off, and the level on the hvc pin is controlled by the pic ? microcontrollers (mcus) io2 pin. when the shdn pin is low, the tc1240a is on and the v out voltage is 2 * v dd . the resistor r 1 allows the hvc pin to go higher than the voltage such that the pic mcu?s io2 pin ?clamps? at approximately v dd . figure 8-1: using the tc1240a to generate the v ihh voltage. the circuit in figure 8-2 shows the method used on the mcp402x non-volatile digital potentiometer evalua- tion board (part number: mcp402xev). this method requires that the system vo ltage be approximately 5v. this ensures that when the pic10f206 enters a brown-out condition, there is an insufficient voltage level on the hvc pin to change the stored value of the wiper. the mcp402x non-volatile digital potentiome- ter evaluation board user?s guide (ds51546) contains a complete schematic. gp0 is a general purpose i/o pin, while gp2 can either be a general purpose i/o pin or it can output the internal clock. for the serial commands, configure the gp2 pin as an input (high impedance). the ou tput state of the gp0 pin will determine the voltage on the hvc pin (v il or v ih ). for high-voltage serial commands, force the gp0 output pin to output a high level (v oh ) and configure the gp2 pin to output the internal clock. this will form a charge pump and increase the voltage on the hvc pin (when the system voltage is approximately 5v). figure 8-2: mcp4xxx non-volatile digital potentiometer evaluation board (mcp402xev) implementation to generate the v ihh voltage. hvc pic mcu mcp45x x r 1 io1 io2 c 2 tc1240a v in shdn c+ c- v out c 1 mcp46xx hvc pic10f206 mcp4xxx r 1 gp0 gp2 c 2 c 1
? 2008 microchip technology inc. ds22091a-page 65 mcp454x/456x/464x/466x 8.2 using shutdown figure 8-3 shows a possible application circuit where the independent terminals could be used. disconnect- ing the wiper allows the transistor input to be taken to the bias voltage level (disconnecting a and or b may be desired to reduce system current). disconnecting terminal a modifies the transistor input by the r bw rheostat value to the co mmon b. disconnecting terminal b modifies the transistor input by the r aw rheostat value to the common a. the common a and common b connections could be connected to v dd and v ss . figure 8-3: example application circuit using terminal disconnects. 8.3 software reset sequence at times it may become nec essary to perform a soft- ware reset sequence to ensure the mcp45xx/46xx device is in a correct and known i 2 c interface state. this technique only resets the i 2 c state machine. this is useful if the mcp45xx/46xx device powers up in an incorrect state (due to excessive bus noise, ...), or if the master device is reset during communication. figure 8-4 shows the communication sequence to soft- ware reset the device. figure 8-4: software reset sequence format. the 1st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. in this mode, the device is monitoring the data bus in receive mode and can detect the start bit forces an internal reset. the nine bits of ?1? are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mcp45xx/46xx is driving an ack on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of ?0? onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the mcp45xx/46xx holding the bus low. by sending out nine ?1? bits, it is ensured that the device will see a nack (the master device does not drive the i 2 c bus low to acknowledge the data sent by the mcp45xx/46xx), which also forces the mcp45xx/46xx to reset. the 2nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while sending a write command to the mcp45xx/46xx, and th en as the master device returns to normal operation and issues a start condition while the mcp45xx/46xx is issuing an ack. in this case, if the 2nd start bit is not sent (and the stop bit was sent) the mcp45xx/46xx could initiate a write cycle. the stop bit terminates the current i 2 c bus activity. the mcp45xx/46xx wait to detect the next start condition. this sequence does not effect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. note: this technique is documented in an1028. balance bias w b input input to b a s e of transistor (or amplifier) a common b common a note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the mcp45xx/46xx. s ?1? ?1? ?1? ?1? ?1? ?1? ?1? ?1? s p start bit nine bits of ?1? start bit stop bit
mcp454x/456x/464x/466x ds22091a-page 66 ? 2008 microchip technology inc. 8.4 using the general call command the use of the general call address increment, decre- ment, or write commands is analogous to the ?load? feature (ldac pin) on some dacs (such as the mcp4921). this allows all the devices to ?update? the output level ?at the same time?. for some applications, the ability to update the wiper values ?at the same time may be a requirement, since they delay from writing to one wiper value and then the next may cause application issues. a possible example would be a ?tuned? circuit that uses several mcp45xx/ 46xx in rheostat configurat ion. as the system condition changes (temperature, load, ...) these devices need to be changed (incremented/decremented) to adjust for the system change. these changes will either be in the same direction or in opposite directions. with the potentiometer device the cu stomer can either select the pxb terminals (same direction) or the pxa terminal(s) (opposite direction). figure 8-6 shows that the update of six devices takes 6*t i2cdly time in ?normal? operation, but only 1*t i2cdly time in ?general call? operation. figure 8-5 shows two i 2 c bus configurations. in many cases, the single i 2 c bus configuration will be adequate. for applications that do not want all the mcp45xx/46xx devices to do general call support or have a conflict with general call commands, the multiple i 2 c bus configuration would be used. figure 8-5: typical application i 2 c bus configurations. figure 8-6: example comparison of ?normal operatio n? vs. ?general call operation? wiper updates. note: the application system may need to partition the i 2 c bus into multiple busses to ensure that the mcp45xx/46xx general call commands do not conflict with the general call commands that the other i 2 c devices may have defined. also if only a portion of the mcp45xx/46xx devices are to require this synchronous operation, then the devices that should not receive these commands should be on the second i 2 c bus. single i 2 c bus configuration host controller device 1 device 3 device n device 2 device 4 multiple i 2 c bus configuration host controller device 1a device 3a device na device 2a device 4a device 1b device 3b device nb device 2b device 4b bus b bus a device 1n device 3n device nn device 2n device 4n bus n normal operation general call operation inc pot01 inc pot02 inc pot03 inc pot04 inc pot05 inc pot06 t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly = time from one i 2 c command completed to completing the next i 2 c command. inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 inc pots 01-06 t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly t i2cdly
? 2008 microchip technology inc. ds22091a-page 67 mcp454x/456x/464x/466x 8.5 design considerations in the design of a system with the mcp4xxx devices, the following considerations should be taken into account: ? power supply considerations ? layout considerations 8.5.1 power supply considerations the typical application will require a bypass capacitor in order to filter high-fr equency noise, which can be induced onto the power supply's traces. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-7 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close (within 4 mm) to the device power pin (v dd ) as possible. the power source supplying these devices should be as clean as possible. if the application circuit has separate digital and analog power supplies, v dd and v ss should reside on the analog plane. figure 8-7: typical microcontroller connections. 8.5.2 layout considerations inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp4xxx?s performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving th e performance that the silicon is capable of providing. particularly harsh environ- ments may require shieldin g of critical signals. if low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.5.3 resistor tempco characterization curves of the resistor temperature coefficient (tempco) are shown in figure 2-10 , figure 2-21 , figure 2-32 , and figure 2-43 . these curves show that the resistor network is designed to correct for the change in resistance as temperature increases. this technique reduces the end to end change is r ab resistance. 8.5.4 high voltage tolerant pins high voltage support (v ihh ) on the serial interface pins supports user configurat ion of the non-volatile eeprom, write protect, and wiperlock feature. v dd v dd v ss v ss mcp454x/456x/ 464x/466x 0.1 f pic ? microcontroller 0.1 f scl sda w b a note: in many applications, the high voltage will only be present at the manufacturing stage so as to ?lock? the non-volatile wiper value (after calibration) and the con- tents of the eeprom. this ensures that the since high voltage is not present under normal operating conditions, that these values can not be modified.
mcp454x/456x/464x/466x ds22091a-page 68 ? 2008 microchip technology inc. 9.0 development support 9.1 development tools several development tools are available to assist in your design and evaluation of the mcp4xxx devices. the currently available tools are shown in ta b l e 9 - 1 . these boards may be purchased directly from the microchip web site at www.microchip.com. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. ta b l e 9 - 2 shows some of these documents. table 9-1: development tools table 9-2: technical documentation board name part # supported devices mcp41xx/42xx pictail plus daughter board (2) mcp4xxxdm-ptpls mcp42xx, mcp46xx mcp4xxx digital potentiometer daughter board (1) mcp4xxxdm-db mcp42xxx, mcp42xx, mcp46xx, mcp4021, and mcp4011 8-pin soic/msop/tssop/dip ev aluation board soic8ev any 8-pin device in dip, soic, msop, or tssop package 14-pin soic/msop/dip evaluation board soic14e v any 14-pin device in dip, soic, or msop package note 1: requires the use of a picdem demo board (see user?s guide for details) 2: requires the use of the pic24 explorer 16 demo board (see user?s guide for details) 3: the desired mcp46xx device (in msop package) must be soldered onto the extra board. application note number title literature # an1080 understanding digital potentiome ters resistor variations ds01080 an737 using digital potentiometers to design low pass adjustable filters ds00737 an692 using a digital potentiometer to optimize a precision single supply photo detect ds00692 an691 optimizing the digital potentiometer in precision circuits ds00691 an219 comparing digital potentiometers to mechanical potentiometers ds00219 ? digital potentiometer design guide ds22017 ? signal chain design guide ds21825
? 2008 microchip technology inc. ds22091a-page 69 mcp454x/456x/464x/466x 10.0 packaging information 10.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead dfn (3x3) example : part number code part number code mcp4541-502e/mf dacj mcp4542-502e/mf dacp mcp4541-103e/mf dack mcp4542-103e/mf dacq mcp4541-104e/mf dacm mcp4542-104e/mf dacs mcp4541-503e/mf dacl mcp4542-503e/mf dacr mcp4561-502e/mf dadb mcp4562-502e/mf dadf mcp4561-103e/mf dadc mcp4562-103e/mf dadg mcp4561-104e/mf dade mcp4562-104e/mf dadj mcp4561-503e/mf dadd mcp4562-503e/mf dadh dacj e823 256 xxxx xyww nnn 8-lead msop xxxxxx ywwnnn example 454113 823256 part number code part number code mcp4541-103e/ms 454113 mcp4542-103e/ms 454213 mcp4541-104e/ms 454114 mcp4542-104e/ms 454214 mcp4541-502e/ms 454152 mcp4542-502e/ms 454252 mcp4541-503e/ms 454153 mcp4542-503e/ms 454253 mcp4561-103e/ms 456113 mcp4562-103e/ms 456213 mcp4561-104e/ms 456114 mcp4562-104e/ms 456214 mcp4561-502e/ms 456152 mcp4562-502e/ms 456252 mcp4561-503e/ms 456153 mcp4562-503e/ms 456253
mcp454x/456x/464x/466x ds22091a-page 70 ? 2008 microchip technology inc. package marking information (continued) 10-lead dfn (3x3) example : part number code part number code mcp4642-502e/mf aafa mcp4662-502e/mf aaqa mcp4642-103e/mf aaga mcp4662-103e/mf aara mcp4642-104e/mf aaja mcp4662-104e/mf aata mcp4642-503e/mf aaha mcp4662-503e/mf aasa aafa 0823 256 xxxx yyww nnn 10-lead msop xxxxxx ywwnnn example 463252 823256 part number code part number code mcp4642-502e/un 464252 mcp4662-502e/un 466252 mcp4642-103e/un 464213 mcp4662-103e/un 466213 mcp4642-104e/un 464214 mcp4662-104e/un 466214 mcp4642-503e/un 464253 mcp4662-503e/un 466253 14-lead tssop (mcp4641, mcp4661) xxxxxxxx yyww nnn example 4641502e 0823 256 xxxxx 16-lead qfn (mcp4641, mcp4661) xxxxxx yywwnnn example xxxxxx 4641 502 823256 e/ml^^ 3 e
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? 2008 microchip technology inc. ds22091a-page 79 mcp454x/456x/464x/466x appendix a: revision history revision a (june 2008) ? original release of this document.
mcp454x/456x/464x/466x ds22091a-page 80 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds22091a-page 81 mcp454x/456x/464x/466x product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp4541: single non-volatile 7-bit potentiometer mcp4541t: single non-volatile 7-bit potentiometer (tape and reel) mcp4542: single non-volatile 7-bit rheostat mcp4542t: single non-volatile 7-bit rheostat (tape and reel) mcp4561: single non-volatile 8-bit potentiometer mcp4561t: single non-volatile 8-bit potentiometer (tape and reel) mcp4562: single non-volatile8-bit rheostat mcp4562t: single non-volatile 8-bit rheostat (tape and reel) mcp4641: dual non-volatile 7-bit potentiometer mcp4641t: dual non-volatile 7-bit potentiometer (tape and reel) mcp4642: dual non-volatile 7-bit rheostat mcp4642t: dual non-volatile 7-bit rheostat (tape and reel) mcp4661: dual non-volatile 8-bit potentiometer mcp4661t: dual non-volatile 8-bit potentiometer (tape and reel) mcp4662: dual non-volatile8-bit rheostat mcp4662t: dual non-volatile 8-bit rheostat (tape and reel) resistance version: 502 = 5 k 103 = 10 k 503 = 50 k 104 = 100 k temperature range: e = -40c to +125c package: mf = plastic dual flat no-lead (3x3 dfn), 8/10-lead ml = plastic quad flat no-lead (qfn), 16-lead ms = plastic micro small outline (msop), 8-lead st = plastic thin shrink small outline (tssop), 14-lead un = plastic micro small outline (msop), 10-lead part no. x /xx package temperature range device examples: a) mcp4541-502e/xx: 5 k , 8ld device b) mcp4541-103e/xx: 10 k , 8-ld device c) mcp4541-503e/xx: 50 k , 8ld device d) mcp4541-104e/xx: 100 k , 8ld device e) mcp4541t-104e/xx: t/r, 100 k , 8ld device a) mcp4542-502e/xx: 5 k , 8ld device b) mcp4542-103e/xx: 10 k , 8-ld device c) mcp4542-503e/xx: 50 k , 8ld device d) mcp4542-104e/xx: 100 k , 8ld device e) mcp4542t-104e/xx: t/r, 100 k , 8ld device a) mcp4561-502e/xx: 5 k , 8ld device b) mcp4561-103e/xx: 10 k , 8-ld device c) mcp4561-503e/xx: 50 k , 8ld device d) mcp4561-104e/xx: 100 k , 8ld device e) mcp4561t-104e/xx: t/r, 100 k , 8ld device a) mcp4562-502e/xx: 5 k , 8ld device b) mcp4562-103e/xx: 10 k , 8-ld device c) mcp4562-503e/xx: 50 k , 8ld device d) mcp4562-104e/xx: 100 k , 8ld device e) mcp4562t-104e/xx: t/r, 100 k , 8ld device a) mcp4641-502e/xx: 5 k , 8ld device b) mcp4641-103e/xx: 10 k , 8-ld device c) mcp4641-503e/xx: 50 k , 8ld device d) mcp4641-104e/xx: 100 k , 8ld device e) mcp4641t-104e/xx: t/r, 100 k , 8ld device a) mcp4642-502e/xx: 5 k , 8ld device b) mcp4642-103e/xx: 10 k , 8-ld device c) mcp4642-503e/xx: 50 k , 8ld device d) mcp4642-104e/xx: 100 k , 8ld device e) mcp4642t-104e/xx: t/r, 100 k , 8ld device a) mcp4661-502e/xx: 5 k , 8ld device b) mcp4661-103e/xx: 10 k , 8-ld device c) mcp4661-503e/xx: 50 k , 8ld device d) mcp4661-104e/xx: 100 k , 8ld device e) mcp4661t-104e/xx: t/r, 100 k , 8ld device a) mcp4662-502e/xx: 5 k , 8ld device b) mcp4662-103e/xx: 10 k , 8-ld device c) mcp4662-503e/xx: 50 k , 8ld device d) mcp4662-104e/xx: 100 k , 8ld device e) mcp4662t-104e/xx: t/r, 100 k , 8ld device xx = mf for 8/10-lead 3x3 dfn = ml for 16-lead qfn = ms for 8-lead msop = st for 14-lead tssop = un for 10-lead msop xxx resistance version
mcp454x/456x/464x/466x ds22091a-page 82 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds22091a-page 83 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microc hip technology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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